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CHAPTER 18
18.4.4 I
2
C bus mode operation
The I
2
C bus mode is provided for when communication operations are performed between a single master device
and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is
based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master
device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data
bus (SDA0 or SDA1) line. Consequently, when the user plans to configure a serial bus which includes multiple
microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port
pins and on-board wires.
In the I
2
C bus specification, the master sends start condition, data, and stop condition signals to slave devices
through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the
signal detection function incorporated as hardware. This simplifies the application program to control I
An example of a serial bus configuration is shown in Figure 18-13. This system below is composed of CPUs and
peripheral ICs having serial interface hardware that complies with the I
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open-
drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I
The signals used in the I
Figure 18-13. Example of Serial Bus Configuration Using I
Master CPU
SDA0 (SDA1)
390
SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
2
C bus mode are described in Table 18-4.
V
DD
Serial clock
SCL
Serial data bus
2
C bus specification.
2
V
DD
Slave CPU1
SCL
SDA0 (SDA1)
Slave CPU2
SCL
SDA0 (SDA1)
Slave IC
SCL
SDA
2
C bus.
2
C bus.
C Bus
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