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1
NEC uPD78078 Computer Hardware manual available for free PDF download: User Manual
NEC uPD78078 User Manual (627 pages)
PD78078 Series; PD78078Y Series 8-bit Single-chip Microcontrollers
Brand:
NEC
| Category:
Computer Hardware
| Size: 2.53 MB
Table of Contents
Table of Contents
13
Chapter 1 Outline ( Pd78078 Subseries)
33
Features
33
Application Fields
34
Ordering Information
34
Quality Grade
35
Pin Configuration (Top View)
36
Series Expansion
42
Block Diagram
44
Outline of Function
45
Mask Options
47
Differences with PD78054 Subseries
47
Mask Options of Mask ROM Versions
47
Differences between PD78078 Subseries and PD78054 Subseries
47
Chapter 2 Outline ( Pd78078Y Subseries)
49
Features
49
Application Fields
50
Ordering Information
50
Quality Grade
51
Pin Configuration (Top View)
52
Series Expansion
58
Block Diagram
60
Outline of Function
61
Mask Options
63
Differences with PD78054Y Subseries
63
Differences between PD78078Y Subseries and PD78054Y Subseries
63
Chapter 3 Pin Function ( Pd78078 Subseries)
65
Pin Function List
65
Normal Operating Mode Pins
65
PROM Programming Mode Pins ( PD78P078 Only)
69
Description of Pin Functions
70
P00 to P07 (Port 0)
70
P10 to P17 (Port 1)
70
P20 to P27 (Port 2)
71
P30 to P37 (Port 3)
72
P40 to P47 (Port 4)
72
P50 to P57 (Port 5)
73
P60 to P67 (Port 6)
73
P70 to P72 (Port 7)
74
P80 to P87 (Port 8)
74
P90 to P96 (Port 9)
75
P100 to P103 (Port 10)
75
P120 to P127 (Port 12)
75
P130 and P131 (Port 13)
76
Av
76
Ref1
76
Av Ref1
76
Av DD
76
Av Ss
76
Reset
76
X1 and X2
76
XT1 and XT2
76
VDD
77
Vss
77
VPP ( PD78P078 Only)
77
IC (Mask ROM Version Only)
77
Input/Output Circuits and Recommended Connection of Unused Pins
78
Pin Input/Output Circuit Types
78
List of Pin Input/Output Circuits
80
Chapter 4 Pin Function ( Pd78078Y Subseries)
83
Pin Function List
83
Normal Operating Mode Pins
83
PROM Programming Mode Pins ( PD78P078Y Only)
87
Description of Pin Functions
88
P00 to P07 (Port 0)
88
P10 to P17 (Port 1)
88
P20 to P27 (Port 2)
89
P30 to P37 (Port 3)
90
P40 to P47 (Port 4)
90
P50 to P57 (Port 5)
91
P60 to P67 (Port 6)
91
P70 to P72 (Port 7)
92
P80 to P87 (Port 8)
92
P90 to P96 (Port 9)
93
P100 to P103 (Port 10)
93
P120 to P127 (Port 12)
93
P130 and P131 (Port 13)
94
Ref0
94
Ref1
94
Av Ref0
94
Av Ref1
94
Av DD
94
Av Ss
94
Reset
94
X1 and X2
94
XT1 and XT2
94
VDD
95
Vss
95
PP ( PD78P078Y Only)
95
IC (Mask ROM Version Only)
95
Input/Output Circuits and Recommended Connection of Unused Pins
96
Pin Input/Output Circuit Types
96
List of Pin Input/Output Circuits
98
Chapter 5 Cpu Architecture
101
Memory Spaces
101
Memory Map ( PD78076, 78076Y)
101
Memory Map ( PD78078, 78078Y)
102
Memory Map ( PD78P078, PD78P078Y)
103
Internal Program Memory Space
104
Internal ROM Capacities
104
Vector Table
105
External Memory Space
106
Internal Data Memory Space
106
Special Function Register (SFR) Area
106
Data Memory Addressing
107
Data Memory Addressing ( PD78078, 78078Y)
108
Data Memory Addressing ( PD78P078, 78P078Y)
109
Processor Registers
110
Control Registers
110
Program Counter Configuration
110
Program Status Word Configuration
110
Data to be Saved to Stack Memory
112
Data to be Reset from Stack Memory
112
General Registers
113
Stack Pointer Configuration
112
General Register Configuration
113
Special Function Register (SFR)
114
Special Function Register List
115
Instruction Address Addressing
118
Relative Addressing
118
Immediate Addressing
119
Table Indirect Addressing
120
Register Addressing
121
Operand Address Addressing
122
Implied Addressing
122
Register Addressing
123
Direct Addressing
124
Short Direct Addressing
125
Special Function Register (SFR) Addressing
126
Register Indirect Addressing
127
Based Addressing
128
Based Indexed Addressing
129
Stack Addressing
129
Chapter 6 Port Functions
131
Port Functions
131
Port Types
131
Port Functions ( PD78078 Subseries)
132
Port Functions ( PD78078Y Subseries)
134
Port Configuration
136
Port 0
136
Block Diagram of P00 and P07
137
Block Diagram of P01 to P06
137
Port 1
138
Block Diagram of P10 to P17
138
Port 2 ( PD78078 Subseries)
139
Block Diagram of P20, P21, P23 to P26
139
Block Diagram of P22 and P27
140
Port 2 ( PD78078Y Subseries)
141
Block Diagram of P20, P21, P23 to P26
141
Block Diagram of P22 and P27
142
Port 3
143
Block Diagram of P30 to P37
143
Port 12
144
Port 4
144
Block Diagram of P40 to P47
144
Block Diagram of Falling Edge Detection Circuit
144
Port 5
145
Block Diagram of P50 to P57
145
Port 6
146
Block Diagram of P60 to P63
147
Block Diagram of P64 to P67
147
Port 7
148
Block Diagram of P70
148
Block Diagram of P71 and P72
149
Port 8
150
Block Diagram of P80 to P87
150
Port 9
151
Block Diagram of P90 to P93
152
Block Diagram of P94 to P96
152
Block Diagram of P100 and P101
153
Port 10
153
Block Diagram of P102 and P103
154
Block Diagram of P120 to P127
155
Port 13
156
Block Diagram of P130 and P131
156
Port Function Control Registers
157
Port Mode Register and Output Latch Settings When Using Alternate Function
158
Port Mode Register Format
159
Pull-Up Resistor Option Register Format
160
Memory Expansion Mode Register Format
161
Key Return Mode Register Format
162
Port Function Operations
163
Operations on Input/Output Port
163
Reading from Input/Output Port
163
Writing to Input/Output Port
163
Comparison between Mask ROM Version and the PD78P078 and 78P078Y
164
Selection of Mask Option
164
Chapter 7 Clock Generator
165
Clock Generator Functions
165
Clock Generator Configuration
166
Block Diagram of Clock Generator
166
Clock Generator Control Register
167
Subsystem Clock Feedback Resistor
167
Processor Clock Control Register Format
168
Relationship between CPU Clock and Minimum Instruction Execution Time
169
Main System Clock Waveform Due to Writing to OSMS
170
Oscillation Mode Selection Register Format
170
System Clock Oscillator
171
Main System Clock Oscillator
171
External Circuit of Main System Clock Oscillator
171
Subsystem Clock Oscillator
172
External Circuit of Subsystem Clock Oscillator
172
Examples of Oscillator with Bad Connection
172
Divider
174
When no Subsystem Clocks Are Used
174
Clock Generator Operations
175
Main System Clock Operations
176
Main System Clock Stop Function
176
Subsystem Clock Operations
177
Changing System Clock and CPU Clock Settings
178
Time Required for Switchover between System Clock and CPU Clock
178
Maximum Time Required for CPU Clock Switchover
178
System Clock and CPU Clock Switching Procedure
179
Chapter 8 16-Bit Timer/Event Counter
181
Outline of Timers Incorporated into PD78078, 78078Y Subseries
181
Timer/Event Counter Operations
182
16-Bit Timer/Event Counter Functions
183
Bit Timer/Event Counter Interval Times
183
Bit Timer/Event Counter Square-Wave Output Ranges
184
16-Bit Timer/Event Counter Configuration
185
Bit Timer/Event Counter Block Diagram
186
Bit Timer/Event Counter Output Control Circuit Block Diagram
187
INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
188
16-Bit Timer/Event Counter Control Registers
190
Timer Clock Selection Register 0 Format
191
Bit Timer Mode Control Register Format
192
Capture/Compare Control Register 0 Format
193
Bit Timer Output Control Register Format
194
Port Mode Register 3 Format
195
External Interrupt Mode Register 0 Format
196
Sampling Clock Select Register Format
197
16-Bit Timer/Event Counter Operations
198
Interval Timer Operations
198
Control Register Settings for Interval Timer Operation
198
Interval Timer Configuration Diagram
199
Interval Timer Operation Timings
199
PWM Output Operations
200
Bit Timer/Event Counter Interval Times
200
Control Register Settings for PWM Output Operation
201
Example of D/A Converter Configuration with PWM Output
202
TV Tuner Application Circuit Example
202
PPG Output Operations
203
Control Register Settings for PPG Output Operation
203
Pulse Width Measurement Operations
204
Configuration Diagram for Pulse Width Measurement by Free-Running Counter
205
Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with both Edges Specified)
205
Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
206
Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
209
Control Register Settings for Pulse Width Measurement by Means of Restart
210
External Event Counter Operation
211
Control Register Settings in External Event Counter Mode
211
External Event Counter Configuration Diagram
212
External Event Counter Operation Timings (with Rising Edge Specified)
212
Square-Wave Output Operation
213
Control Register Settings in Square-Wave Output Mode
213
Bit Timer/Event Count Square-Wave Output Ranges
214
One-Shot Pulse Output Operation
215
Square-Wave Output Operation Timing
214
Timing of One-Shot Pulse Output Operation Using Software Trigger
216
Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
217
16-Bit Timer/Event Counter Operating Precautions
219
Bit Timer Register Start Timing
219
Timings after Change of Compare Register During Timer Count Operation
219
Capture Register Data Retention Timing
220
Operation Timing of OVF0 Flag
221
Chapter 9 8-Bit Timer/Event Counters 1 and 2
223
8-Bit Timer/Event Counters 1 and 2 Functions
223
8-Bit Timer/Event Counter Mode
223
Bit Timer/Event Counters 1 and 2 Interval Times
224
Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
225
16-Bit Timer/Event Counter Mode
226
Are Used as 16-Bit Timer/Event Counters
226
Interval Times When 8-Bit Timer/Event Counters 1 and
226
Square-Wave Output Ranges When 8-Bit Timer/Event Counters 1 and 2 Are Used as 16-Bit Timer/Event Counters
227
8-Bit Timer/Event Counters 1 and 2 Configurations
228
Bit Timer/Event Counters 1 and 2 Block Diagram
228
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
229
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2
229
8-Bit Timer/Event Counters 1 and 2 Control Registers
231
Timer Clock Select Register 1 Format
232
Bit Timer Mode Control Register 1 Format
233
Bit Timer Output Control Register Format
234
Port Mode Register 3 Format
235
8-Bit Timer/Event Counters 1 and 2 Operations
236
8-Bit Timer/Event Counter Mode
236
Interval Timer Operation Timing
236
Bit Timer/Event Counter 1 Interval Time
237
Bit Timer/Event Counter 2 Interval Time
238
External Event Counter Operation Timings (with Rising Edge Specified)
239
Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges
240
Timing of Square Wave Output Operation
241
16-Bit Timer/Event Counter Mode
242
Interval Timer Operation Timing
242
Are Used as 16-Bit Timer/Event Counter
243
External Event Counter Operation Timings (with Rising Edge Specified)
244
Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters TM1 and TM2) Are Used as 16-Bit Timer/Event Counter
245
8-Bit Timer/Event Counters 1 and 2 Precautions
246
Bit Timer Registers 1 and 2 Start Timing
246
External Event Counter Operation Timing
246
Timing after Compare Register Change During Timer Count Operation
247
Chapter 10 8-Bit Timer/Event Counters 5 and 6
249
8-Bit Timer/Event Counters 5 and 6 Functions
249
Bit Timer/Event Counters 5 and 6 Interval Times
250
Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
251
8-Bit Timer/Event Counters 5 and 6 Configurations
252
Bit Timer/Event Counters 5 and 6 Block Diagram
252
Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit
253
8-Bit Timer/Event Counters 5 and 6 Control Registers
254
Timer Clock Select Register 5 Format
254
Timer Clock Select Register 6 Format
255
Bit Timer Output Control Register Format
256
Bit Timer Output Control Register 6 Format
257
Port Mode Register 10 Format
258
8-Bit Timer/Event Counters 5 and 6 Operations
259
Interval Timer Operations
259
Bit Timer Mode Control Register Settings for Interval Timer Operation
259
Interval Timer Operation Timings
259
Bit Timer/Event Counters 5 and 6 Interval Times
260
Bit Timer Mode Control Register Setting for External Event Counter Operation
261
External Event Counter Operation
261
Square-Wave Output
262
Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
263
PWM Output Operations
264
Bit Timer Control Register Settings for PWM Output Operation
264
PWM Output Operation Timing (Active High Setting)
265
PWM Output Operation Timings (Crn0 = 00H, Active High Setting)
265
PWM Output Operation Timings (Crn0 Changing, Active High Setting)
266
8-Bit Timer/Event Counters 5 and 6 Precautions
267
Bit Timer Registers 5 and 6 Start Timings
267
External Event Counter Operation Timings
267
Timings after Compare Register Change During Timer Count Operation
268
Chapter 11 Watch Timer
269
Watch Timer Functions
269
Interval Timer Interval Time
269
Watch Timer Configuration
270
Watch Timer Control Registers
271
Watch Timer Block Diagram
271
Timer Clock Select Register 2 Format
272
Watch Timer Mode Control Register Format
273
Watch Timer Operations
274
Watch Timer Operation
274
Interval Timer Operation
274
Interval Timer Interval Time
274
Chapter 12 Watchdog Timer
275
Watchdog Timer Functions
275
Interval Times
276
Watchdog Timer Configuration
277
Watchdog Timer Block Diagram
277
Watchdog Timer Control Registers
278
Timer Clock Select Register 2 Format
279
Watchdog Timer Mode Register Format
280
Watchdog Timer Operations
281
Watchdog Timer Operation
281
Watchdog Timer Runaway Detection Times
281
Interval Timer Interval Time
282
Interval Timer Operation
282
Chapter 13 Clock Output Control Circuit
283
Clock Output Control Circuit Functions
283
Remote Controlled Output Application Example
283
Clock Output Control Circuit Configuration
284
Clock Output Control Circuit Block Diagram
284
Clock Output Function Control Registers
285
Timer Clock Select Register 0 Format
286
Port Mode Register 3 Format
287
Chapter 14 Buzzer Output Control Circuit
289
Buzzer Output Control Circuit Functions
289
Buzzer Output Control Circuit Configuration
289
Buzzer Output Control Circuit Block Diagram
289
Buzzer Output Function Control Registers
290
Timer Clock Select Register 2 Format
291
Port Mode Register 3 Format
292
Chapter 15 A/D Converter
293
A/D Converter Functions
293
A/D Converter Configuration
293
A/D Converter Block Diagram
294
A/D Converter Control Registers
296
A/D Converter Mode Register Format
297
A/D Converter Input Select Register Format
298
External Interrupt Mode Register 1 Format
299
A/D Converter Operations
300
Basic Operations of A/D Converter
300
A/D Converter Basic Operation
301
Input Voltage and Conversion Results
302
Relationships between Analog Input Voltage and A/D Conversion Result
302
A/D Converter Operating Mode
303
A/D Conversion by Hardware Start
303
A/D Conversion by Software Start
304
A/D Converter Cautions
305
Example of Method of Reducing Current Consumption in Standby Mode
305
Analog Input Pin Disposition
306
A/D Conversion End Interrupt Request Generation Timing
307
Chapter 16 D/A Converter
309
D/A Converter Functions
309
D/A Converter Configuration
310
D/A Converter Block Diagram
310
D/A Converter Control Registers
312
D/A Converter Mode Register Format
312
D/A Converter Operations
313
D/A Converter Cautions
314
Use Example of Buffer Amplifier
314
Chapter 17 Serial Interface Channel 0 ( Pd78078 Subseries)
315
Differences between Channels 0, 1, and 2
315
Serial Interface Channel 0 Functions
316
Serial Bus Interface (SBI) System Configuration Example
317
Serial Interface Channel 0 Configuration
318
Serial Interface Channel 0 Block Diagram
318
Serial Interface Channel 0 Control Registers
321
Timer Clock Select Register 3 Format
322
Serial Operating Mode Register 0 Format
324
Serial Bus Interface Control Register Format
325
Interrupt Timing Specify Register Format
327
Serial Interface Channel 0 Operations
328
Operation Stop Mode
328
3-Wire Serial I/O Mode Operation
329
RELT and CMDT Operations
331
Wire Serial I/O Mode Timings
331
Circuit of Switching in Transfer Bit Order
332
SBI Mode Operation
333
Example of Serial Bus Configuration with SBI
333
SBI Transfer Timings
335
Bus Release Signal
336
Command Signal
336
Addresses
337
Slave Selection with Address
337
Commands
338
Data
338
Acknowledge Signal
339
BUSY and READY Signals
339
RELT, CMDT, RELD, and CMDD Operations (Master)
344
ACKT Operation
345
ACKE Operations
346
ACKD Operations
347
BSYE Operation
347
Various Signals in SBI Mode
348
Pin Configuration
350
Address Transmission from Master Device to Slave Device (WUP = 1)
352
Command Transmission from Master Device to Slave Device
353
Data Transmission from Master Device to Slave Device
354
Data Transmission from Slave Device to Master Device
355
2-Wire Serial I/O Mode Operation
357
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
357
RELT and CMDT Operations
361
Wire Serial I/O Mode Timings
361
SCK0/P27 Pin Configuration
363
SCK0/P27 Pin Output Manipulation
363
CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( PD78078Y Subseries)
365
Differences between Channels 0, 1, and 2
365
Serial Interface Channel 0 Functions
366
Serial Interface Channel 0 Configuration
368
Serial Interface Channel 0 Block Diagram
369
Serial Interface Channel 0 Interrupt Request Signal Generation
371
Serial Interface Channel 0 Control Registers
372
Timer Clock Select Register 3 Format
373
Serial Operating Mode Register 0 Format
375
Serial Bus Interface Control Register Format
376
Interrupt Timing Specify Register Format
378
Serial Interface Channel 0 Operations
380
Operation Stop Mode
380
3-Wire Serial I/O Mode Operation
381
Wire Serial I/O Mode Timings
383
RELT and CMDT Operations
383
Circuit of Switching in Transfer Bit Order
384
2-Wire Serial I/O Mode Operation
385
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
385
Wire Serial I/O Mode Timings
388
RELT and CMDT Operations
389
C Bus Mode Operation
390
I 2 C Bus Serial Data Transfer Timing
391
Start Condition
392
Address
392
Transfer Direction Specification
392
Stop Condition
393
Acknowledge Signal
393
Wait Signal
394
Pin Configuration
399
Cautions on Use of I C Bus Mode
408
Start Condition Output
408
Slave Wait Release (Transmission)
409
Slave Wait Release (Reception)
410
Restrictions in I 2 C Bus Mode
411
Restrictions in I C Bus Mode
411
SCK0/SCL/P27 Pin Configuration
413
SCK0/SCL/P27 Pin Output Manipulation
413
SCK0/SCL/P27 Pin Configuration
414
Logic Circuit of SCL Signal
414
Chapter 19 Serial Interface Channel 1
415
Serial Interface Channel 1 Functions
415
Serial Interface Channel 1 Configuration
416
Serial Interface Channel 1 Block Diagram
416
Serial Interface Channel 1 Control Registers
418
Timer Clock Select Register 3 Format
418
Serial Operation Mode Register 1 Format
419
Automatic Data Transmit/Receive Control Register Format
420
Automatic Data Transmit/Receive Interval Specify Register Format
421
Serial Interface Channel 1 Operations
425
Operation Stop Mode
425
3-Wire Serial I/O Mode Operation
426
Wire Serial I/O Mode Timings
427
Circuit of Switching in Transfer Bit Order
428
3-Wire Serial I/O Mode Operation with Automatic Transmit/Receive Function
429
Basic Transmission/Reception Mode Operation Timings
436
Basic Transmission/Reception Mode Flowchart
437
Basic Transmission Mode Operation Timings
440
Basic Transmission Mode Flowchart
441
Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode)
443
Repeat Transmission Mode Operation Timing
444
Repeat Transmission Mode Flowchart
445
Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode)
447
Automatic Transmission/Reception Suspension and Restart
448
System Configuration When the Busy Control Option Is Used
449
Operation Timings When Using Busy Control Option (BUSY0 = 0)
450
Busy Signal and Wait Cancel (BUSY0 = 0)
451
Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)
452
Automatic Data Transmit/Receive Interval
454
Interval Timing through CPU Processing (When the Internal Clock Is Operating)
455
Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
455
Interval Timing through CPU Processing (When the External Clock Is Operating)
456
Chapter 20 Serial Interface Channel 2
457
Serial Interface Channel 2 Functions
457
Serial Interface Channel 2 Configuration
458
Serial Interface Channel 2 Block Diagram
458
Baud Rate Generator Block Diagram
459
Serial Interface Channel 2 Control Registers
461
Serial Operating Mode Register 2 Format
461
Asynchronous Serial Interface Mode Register Format
462
Serial Interface Channel 2 Operating Mode Settings
463
Asynchronous Serial Interface Status Register Format
464
Baud Rate Generator Control Register Format
465
Relationship between Main System Clock and Baud Rate
467
Serial Interface Channel 2 Operation
469
Operation Stop Mode
469
Asynchronous Serial Interface (UART) Mode
471
Relationship between Main System Clock and Baud Rate
476
Asynchronous Serial Interface Transmit/Receive Data Format
478
Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
480
Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
481
Receive Error Causes
482
Receive Error Timing
482
State of Receive Buffer Register (RXB) When Receive Operation Is Stopped and Whether Interrupt Request (INTSR) Is Generated or Not
483
3-Wire Serial I/O Mode
484
Wire Serial I/O Mode Timing
489
Circuit of Switching in Transfer Bit Order
490
Restrictions on Using UART Mode
491
Receive Completion Interrupt Request Generation Timing (ISRM = 1)
491
Period that Reading Receive Buffer Register Is Prohibited
492
Chapter 21 Real-Time Output Port
495
Real-Time Output Port Functions
495
Real-Time Output Port Block Diagram
495
Real-Time Output Port Configuration
495
Operation in Real-Time Output Buffer Register Manipulation
496
Real-Time Output Port Control Registers
497
Real-Time Output Buffer Register Configuration
496
Port Mode Register 12 Format
497
Real-Time Output Port Mode Register Format
497
Real-Time Output Port Control Register Format
498
Real-Time Output Port Operating Mode and Output Trigger
498
Chapter 22 Interrupt Functions
499
Interrupt Function Types
499
Interrupt Sources and Configuration
500
Interrupt Source List
500
Basic Configuration of Interrupt Function
502
Interrupt Function Control Registers
504
Various Flags Corresponding to Interrupt Request Sources
504
Interrupt Request Flag Register Format
505
Interrupt Mask Flag Register Format
506
Priority Specify Flag Register Format
507
External Interrupt Mode Register 0 Format
508
External Interrupt Mode Register 1 Format
509
Sampling Clock Select Register Format
510
Noise Eliminator Input/Output Timing (During Rising Edge Detection)
511
Program Status Word Format
512
Interrupt Servicing Operations
513
Non-Maskable Interrupt Request Acknowledge Operation
513
Flowchart from Non-Maskable Interrupt Generation to Acknowledge
514
Non-Maskable Interrupt Request Acknowledge Timing
514
Non-Maskable Interrupt Request Acknowledge Operation
515
Maskable Interrupt Request Acknowledge Operation
516
Times from Maskable Interrupt Request Generation to Interrupt Service
516
Interrupt Request Acknowledge Processing Algorithm
517
Software Interrupt Request Acknowledge Operation
518
Interrupt Request Acknowledge Timing (Maximum Time)
518
Multiple Interrupt Servicing
519
Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing
519
Multiple Interrupt Example
520
Interrupt Request Reserve
522
Interrupt Request Hold
522
Test Functions
523
Basic Configuration of Test Function
523
Flags Corresponding to Test Input Signals
523
Registers Controlling the Test Function
523
Test Input Factors
523
Format of Interrupt Mask Flag Register 1L
524
Test Input Signal Acknowledge Operation
525
Format of Interrupt Request Flag Register 1L
524
Key Return Mode Register Format
525
Chapter 23 External Device Expansion Function
527
External Device Expansion Functions
527
Pin Functions in External Memory Expansion Mode
527
State of Port 4 to Port 6 Pins in External Memory Expansion Mode
527
Pin Functions in Separate Bus Mode
528
State of Port 4 to Port 6 and Port 8 Pins in Separate Bus Mode
528
Memory Map When Using External Device Expansion Function
529
External Device Expansion Function Control Register
531
Memory Expansion Mode Register Format
531
Internal Memory Size Switching Register Format
532
Values When the Internal Memory Size Switching Register Is Reset
532
External Bus Type Select Register Format
533
External Device Expansion Function Timing
534
Timings in Multiplexed Bus Mode
534
Instruction Fetch from External Memory in Multiplexed Bus Mode
535
External Memory Read Timing in Multiplexed Bus Mode
536
External Memory Write Timing in Multiplexed Bus Mode
537
External Memory Read Modify Write Timing in Multiplexed Bus Mode
538
Timings in Separate Bus Mode
539
Instruction Fetch from External Memory in Separate Bus Mode
540
External Memory Read Timing in Separate Bus Mode
541
External Memory Write Timing in Separate Bus Mode
542
External Memory Read Modify Write Timing in Separate Bus Mode
543
Chapter 24 Standby Function
545
Standby Function and Configuration
545
Standby Function
545
Standby Function Control Register
546
Oscillation Stabilization Time Select Register Format
546
Standby Function Operations
547
HALT Mode
547
HALT Mode Released by Interrupt Request Generation
548
HALT Mode Released by RESET Input
549
Operation after HALT Mode Release
549
STOP Mode
550
STOP Mode Released by Interrupt Request Generation
551
Operation after STOP Mode Release
552
STOP Mode Released by RESET Input
552
Chapter 25 Reset Function
553
Reset Function
553
Block Diagram of Reset Function
553
Timing of Reset by RESET Input
554
Timing of Reset Due to Watchdog Timer Overflow
554
Timing of Reset by RESET Input in STOP Mode
554
Hardware Status after Reset
555
Chapter 26 Rom Correction
559
ROM Correction Functions
559
ROM Correction Configuration
559
Block Diagram of ROM Correction
559
Correction Address Registers 0 and 1 Format
560
ROM Correction Control Registers
561
Correction Control Register Format
561
ROM Correction Application
562
Connecting Example with EEPROM (Using 2-Wire Serial I/O Mode)
562
Storing Example to EEPROM (When One Place Is Corrected)
562
Initialization Routine
563
ROM Correction Operation
564
ROM Correction Example
565
Program Execution Flow
566
Program Transition Diagram (When One Place Is Corrected)
566
Program Transition Diagram (When Two Places Are Corrected)
567
Cautions on ROM Correction
568
Chapter 27 Pd78P078, 78P078Y
569
Differences between PROM and Mask ROM Versions
569
Internal Memory Size Switching Register
570
Examples of Internal Memory Size Switching Register Settings
570
Examples of Internal Extension RAM Size Switching Register Settings
571
Internal Extension RAM Size Switching Register
571
PROM Programming
572
Operating Modes
572
PROM Programming Operating Modes
572
PROM Write Procedure
574
Page Program Mode Flowchart
574
Page Program Mode Timing
575
Byte Program Mode Flowchart
576
Byte Program Mode Timing
577
PROM Reading Procedure
578
PROM Read Timing
578
Erasure Procedure ( PD78P078KL-T and 78P078YKL-T Only)
579
Opaque Film Masking Window ( PD78P078KL-T and 78P078YKL-T Only)
579
Screening of One-Time PROM Versions
579
Chapter 28 Instruction Set
581
Legends Used in Operation List
582
Operand Identifiers and Description Methods
582
Description of "Operation" Column
583
Description of "Flag Operation" Column
583
Operation List
584
Instructions Listed by Addressing Type
592
Appendix A Differences between Pd78078, 78075B Subseries, and Pd78070A
597
APPENDIX A DIFFERENCES between Μpd78078, 78075B SUBSERIES, and Μpd78070A
599
Appendix B Development Tools
599
B-1 Development Tool Configuration
600
Language Processing Software
602
PROM Writing Tools
604
Hardware
604
Software
604
B.2.1 Hardware
604
B.2.2 Software
604
Debugging Tools
605
Hardware
605
B.3 Debugging Tools
605
B.3.1 Hardware
605
Software
607
B.3.2 Software
607
OS for IBM PC
609
System Upgrading from Former-Type In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
609
B-2 TGC-100SDW Drawing (for Reference Only)
610
B-3 EV-9200GF-100 Drawing (for Reference Only)
611
B-4 EV-9200GF-100 Recommended Footprints (for Reference Only)
612
Appendix C Embedded Software
613
Appendix D Register Index
615
Register Name Index
615
Register Symbol Index
619
Appendix Erevision History
623
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