Motorola MVME5100 Series Manuals

Manuals and User Guides for Motorola MVME5100 Series. We have 5 Motorola MVME5100 Series manuals available for free PDF download: Programmer's Reference Manual, Manual, Installation & Use Manual, Specification Sheet

Motorola MVME5100 Series Programmer's Reference Manual (320 pages)

Brand: Motorola | Category: Motherboard | Size: 1.35 MB

Table of Contents
7
About this Manual

21
- Overview of Contents
  24
- Summary of Changes
  24
- Comments and Suggestions
  25
- Conventions Used in this Manual
  26
  - Terminology
    26
CHAPTER 1 Product Data and Memory Maps

29
- Introduction
  29
- Table 1-1. MVME Key Features
  29
- Figure 1-1. MVME5100 Block Diagram
  31
- Memory Maps
  32
  - Processor Memory Map
    32
    
    Default Processor Memory Map
    32
    
    Table 1-2. Default Processor Memory Map
    32
    
    Processor Memory Map
    33
    
    Table 1-3. Suggested CHRP Memory Map
    34
    
    PCI Memory Map
    35
    
    VME Memory Map
    35
    
    Table 1-4. Hawk PPC Register Values for Suggested Memory Map
    35
  - PCI Local Bus Memory Map
    36
  - Vmebus Memory Map
    36
- System Bus
  36
  - Processors
    37
  - Processor Type Identification
    37
  - Processor PLL Configuration
    37
  - L2 Cache
    37
  - L2 Cache SRAM Size
    38
  - Cache Speed
    38
  - FLASH Memory
    38
  - ECC Memory
    39
  - P2 I/O Modes
    39
  - Serial Presence Detect (SPD) Definitions
    40
- Hawk ASIC
  40
- PCI Local Bus
  43
CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

63
- Introduction
  63
  - Overview
    63
  - Features
    63
- Block Diagram
  65
- Figure 2-1. Hawk PCI Host Bridge Block Diagram
  65
- Functional Description
  66
  - Architectural Overview
    66
  - PPC Bus Interface
    67
    
    PPC Address Mapping
    68
    
    Figure 2-2. PPC to PCI Address Decoding
    68
    
    PPC Slave
    69
    
    Figure 2-3. PPC to PCI Address Translation
    69
    
    Table 2-1. PPC Slave Response Command Types
    70
    
    Ppc Fifo
    71
    
    PPC Master
    72
    
    Table 2-2. PPC Master Transaction Profiles and Starting Offsets
    73
    
    Table 2-3. PPC Master Write Posting Options
    74
    
    Table 2-4. PPC Master Read Ahead Options
    74
    
    Table 2-5. PPC Master Transfer Types
    76
    
    PPC Arbiter
    77
    
    Table 2-6. PPC Arbiter Pin Assignments
    77
    
    PPC Parity
    79
    
    PPC Bus Timer
    80
  - PCI Bus Interface
    81
    
    PCI Address Mapping
    81
    
    Figure 2-4. PCI to PPC Address Decoding
    82
    
    Figure 2-5. PCI to PPC Address Translation
    83
    
    PCI Slave
    84
    
    Table 2-7. PCI Slave Response Command Types
    85
    
    Pci Fifo
    88
    
    PCI Master
    88
    
    Table 2-8. PCI Master Command Codes
    89
    
    Generating PCI Cycles
    91
    
    Figure 2-6. PCI Spread I/O Address Translation
    93
    
    PCI Arbiter
    96
    
    Table 2-9. PCI Arbiter Pin Description
    96
    
    Table 2-10. Fixed Mode Priority Level Setting
    97
    
    Table 2-11. Mixed Mode Priority Level Setting
    98
    
    Table 2-12. Arbitration Setting
    99
  - Endian Conversion
    100
    
    When PPC Devices Are Big-Endian
    100
    
    When PPC Devices Are Little Endian
    101
    
    Figure 2-7. Big-To-Little-Endian Data Swap
    101
    
    PHB Registers
    102
    
    Table 2-13. Address Modification for Little Endian Transfers
    102
  - Error Handling
    103
  - Watchdog Timers
    104
  - Table 2-14. Wdtxcntl Programming
    106
  - PCI/PPC Contention Handling
    107
  - Transaction Ordering
    110
  - PHB Hardware Configuration
    111
  - Table 2-15. PHB Hardware Configuration
    112
- Multi-Processor Interrupt Controller (MPIC)
  113
  - MPIC Features
    113
  - Architecture
    113
  - External Interrupt Interface
    114
  - Figure 2-8. Serial Mode Interrupt Scan
    114
  - Csr's Readability
    115
  - Interrupt Source Priority
    115
  - Processor's Current Task Priority
    116
  - Nesting of Interrupt Events
    116
  - Spurious Vector Generation
    116
  - Interprocessor Interrupts (IPI)
    117
  - 8259 Compatibility
    117
  - Hawk Internal Errror Interrupt
    117
  - Timers
    118
  - Interrupt Delivery Modes
    118
  - Block Diagram Description
    119
    
    Figure 2-9. MPIC Block Diagram
    120
    
    Interrupt Pending Register (IPR)
    121
    
    Interrupt Selector (IS)
    121
    
    Program Visible Registers
    121
    
    In-Service Register (ISR)
    122
    
    Interrupt Request Register (IRR)
    122
    
    Interrupt Router
    122
  - Programming Notes
    124
    
    External Interrupt Service
    124
    
    Reset State
    125
  - Operation
    126
    
    Interprocessor Interrupts
    126
    
    Dynamically Changing I/O Interrupt Configuration
    126
    
    EOI Register
    127
    
    Interrupt Acknowledge Register
    127
    
    8259 Mode
    127
    
    Current Task Priority Level
    127
  - Architectural Notes
    128
  - Effects of Interrupt Serialization
    128
- Registers
  129
- PPC Registers
  130
  - Table 2-16. PPC Register Map for PHB
    130
  - Revision ID Register
    132
  - Vendor ID/Device ID Registers
    132
  - General Control-Status/Feature Registers
    133
  - PPC Arbiter/Pci Arbiter Control Registers
    135
  - Hardware Control-Status/Prescaler Adjust Register
    139
  - PPC Error Test/Error Enable Register
    141
  - PPC Error Status Register
    144
  - PPC Error Address Register
    146
  - PPC Error Attribute Register
    147
  - PCI Interrupt Acknowledge Register
    149
  - PPC Slave Address (0,1 and 2) Registers
    150
  - PPC Slave Offset/Attribute (0, 1 and 2) Registers
    151
  - PPC Slave Address (3) Register
    152
  - PPC Slave Offset/Attribute (3) Registers
    153
  - Wdtxcntl Registers
    154
  - General Purpose Registers
    158
  - Wdtxstat Registers
    158
- PCI Registers
  159
  - Table 2-17. PCI Configuration Register
    159
  - Table 2-18. PCI I/O Register
    160
  - Vendor ID/ Device ID Registers
    160
  - PCI Command/ Status Registers
    161
  - Revision ID/ Class Code Registers
    163
  - MPIC I/O Base Address Register
    164
  - MPIC Memory Base Address Register
    164
  - PCI Slave Address (0,1,2, and 3) Registers
    165
  - PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
    166
  - CONFIG_ADDRESS Register
    168
  - CONFIG_DATA Register
    171
- MPIC Registers
  172
  - Feature Reporting Register 0
    172
  - Global Configuration Register
    172
  - Table 2-19. MPIC Register Map
    173
  - Table 2-20. Cascade Mode Encoding
    177
  - Table 2-21. Tie Mode Encoding
    177
  - Vendor Identification Register
    178
  - Processor Init Register
    178
  - IPI Vector/Priority Registers
    179
  - Spurious Vector Register
    180
  - Timer Frequency Register
    180
  - Timer Current Count Registers
    181
  - Timer Basecount Registers
    182
  - Timer Vector/Priority Registers
    183
  - Timer Destination Registers
    184
    
    External Source Vector/Priority Registers
    184
    
    External Source Destination Registers
    186
    
    Hawk Internal Error Interrupt Vector/Priority Register
    187
    
    Hawk Internal Error Interrupt Destination Register
    188
    
    Interprocessor Interrupt Dispatch Registers
    188
    
    Current Task Priority Registers
    189
    
    Interrupt Acknowledge Registers
    189
    
    End-Of-Interrupt Registers
    190
CHAPTER 3 System Memory Controller (SMC)

191
- Introduction
  191
  - Overview
    191
  - Bit Ordering Convention
    191
  - Features
    191
- Block Diagrams
  192
- Figure 3-1. Hawk Used with Synchronous DRAM in a System
  192
- Figure 3-2. Hawk's System Memory Controller Internal Data Paths
  193
- Figure 3-3. Overall SDRAM Connections (4 Blocks Using Register Buffers)
  194
- Figure 3-4. Hawk's System Memory Controller Block Diagram
  195
- Functional Description
  196
  - SDRAM Accesses
    196
    
    Four-Beat Reads/Writes
    196
    
    Single-Beat Reads/Writes
    196
    
    Address Pipelining
    196
    
    Page Holding
    197
    
    SDRAM Speeds
    197
    
    Table 3-1. 60X Bus to SDRAM Estimated Access Timing at 100 Mhz with PC100
    197
  - SDRAM Organization
    199
  - Ppc60X Bus Interface
    199
    
    Responding to Address Transfers
    199
    
    Completing Data Transfers
    199
    
    Ppc60X Data Parity
    200
    
    Ppc60X Address Parity
    200
    
    Cache Coherency
    201
    
    Cache Coherency Restrictions
    201
    
    L2 Cache Support
    201
  - Sdram Ecc
    201
    
    Cycle Types
    201
    
    Error Reporting
    202
    
    Table 3-2. Error Reporting
    202
    
    Error Logging
    203
  - Rom/Flash Interface
    204
    
    Table 3-3. Ppc60X to Rom/Flash (16 Bit Width)
    206
    
    Table 3-4. Ppc60X to Rom/Flash (64 Bit Width) Address Mapping
    207
    
    Rom/Flash Speeds
    209
    
    Table 3-5. Ppc60X Bus to Rom/Flash Access Timing (120Ns @ 100 Mhz)
    209
    
    Table 3-6. Ppc60X Bus to Rom/Flash Access Timing (80Ns @ 100 Mhz)
    210
    
    Table 3-7. Ppc60X Bus to Rom/Flash Access Timing (50Ns @ 100 Mhz)
    210
    
    Table 3-8. Ppc60X Bus to Rom/Flash Access Timing (30Ns @ 100 Mhz)
    211
  - I2C Interface
    212
    
    I2C Byte Write
    213
    
    Figure 3-5. Programming Sequence for I2C Byte Write
    214
    
    I2C Current Address Read
    217
    
    I2C
    219
    
    I2C Sequential Read
    221
  - Refresh/Scrub
    224
  - CSR Accesses
    224
  - External Register Set
    224
  - Chip Configuration
    225
- Programming Model
  225
  - CSR Architecture
    225
  - Register Summary
    226
  - Table 3-9. Register Summary
    226
  - Detailed Register Bit Descriptions
    228
    
    Vendor/Device Register
    229
    
    Revision ID/General Control Register
    229
    
    SDRAM Enable and Size Register (Blocks A, B, C, D)
    231
    
    Table 3-10. Block_A/B/C/D/E/F/G/H Configurations
    232
    
    SDRAM Base Address Register (Blocks A/B/C/D)
    233
    
    CLK Frequency Register
    234
    
    ECC Control Register
    235
    
    Figure 3-10. Read/Write Check-Bit Data Paths
    236
    
    Error Logger Register
    239
    
    Error_Address Register
    241
    
    Scrub/Refresh Register
    241
    
    Scrub Address Register
    242
    
    ROM a Base/Size Register
    243
    
    Table 3-11. ROM Block a Size Encoding
    244
    
    Table 3-13. Read/Write to Rom/Flash
    245
    
    ROM B Base/Size Register
    246
    
    Table 3-14. ROM Block B Size Encoding
    247
    
    ROM Speed Attributes Registers
    248
    
    Table 3-15. ROM Speed Bit Encodings
    249
    
    Data Parity Error Log Register
    250
    
    Data Parity Error Address Register
    251
    
    Data Parity Error Upper Data Register
    251
    
    Data Parity Error Lower Data Register
    252
    
    I2C Transmitter Data Register
    255
    
    I2C Receiver Data Register
    256
    
    SDRAM Enable and Size Register (Blocks E,F,G,H)
    256
    
    SDRAM Base Address Register (Blocks E/F/G/H)
    257
    
    SDRAM Speed Attributes Register
    258
    
    Table 3-16. Trc Encoding
    259
    
    Table 3-17. tras Encoding
    259
    
    Address Parity Error Log Register
    260
    
    Address Parity Error Address Register
    261
    
    32-Bit Counter
    262
    
    External Register Set
    262
    
    Tben Register
    263
- Software Considerations
  264
- ECC Codes
  276
- Table 3-21. Syndrome Codes Ordered by Bit in Error
  276
- Table 3-22. Single Bit Errors Ordered by Syndrome Code
  277
CHAPTER 4 Hawk Programming Details

279
- Introduction
  279
- PCI Arbitration
  279
- Exceptions
  283
  - Sources of Reset
    283
  - CPU Reset
    283
  - Soft Reset
    283
  - Error Notification and Handling
    284
  - Table 4-3. Error Notification and Handling
    284
- Endian Issues
  285
  - Figure 4-1. Big-Endian Mode
    285
  - Figure 4-2. Little-Endian Mode
    286
  - Mpic's Involvement
    287
  - PCI Domain
    287
  - Processor/Memory Domain
    287

Motorola MVME5100 Series Programmer's Reference Manual (270 pages)

Brand: Motorola | Category: Motherboard | Size: 2.67 MB

Table of Contents
10
CHAPTER 1 Product Data and Memory Maps

20
- Introduction
  20
- Memory Maps
  23
  - Processor Memory Map
    23
  - PCI / VME Memory Map
    23
- System Bus
  23
  - Processors
    23
  - Processor Type Identification
    23
  - Processor PLL Configuration
    24
  - L2 Cache
    24
  - L2 Cache SRAM Size
    24
  - Cache Speed
    24
  - Flash Memory
    24
  - System Memory
    25
  - Serial Presence Detect (SPD) Definitions
    25
- Hawk ASIC
  25
- Interrupt Handling
  38
  - Hawk MPIC
    38
  - Table 1-12. Hawk MPIC Interrupt Assignments
    38
CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

40
- Introduction
  40
  - Overview
    40
  - Features
    40
- Block Diagram
  42
- Figure 2-1. Hawk PCI Host Bridge Block Diagram
  42
- Functional Description
  43
  - Architectural Overview
    43
  - PPC Bus Interface
    44
    
    PPC Address Mapping
    45
    
    Figure 2-2. PPC to PCI Address Decoding
    45
    
    PPC Slave
    46
    
    Figure 2-3. PPC to PCI Address Translation
    46
    
    Table 2-1. PPC Slave Response Command Types
    47
    
    Ppc Fifo
    48
    
    PPC Master
    49
    
    Table 2-2. PPC Master Transaction Profiles and Starting Offsets
    50
    
    Table 2-3. PPC Master Write Posting Options
    51
    
    Table 2-4. PPC Master Read Ahead Options
    51
    
    Table 2-5. PPC Master Transfer Types
    53
    
    PPC Arbiter
    54
    
    Table 2-6. PPC Arbiter Pin Assignments
    54
    
    PPC Parity
    56
    
    PPC Bus Timer
    57
  - PCI Bus Interface
    58
    
    PCI Address Mapping
    58
    
    Figure 2-4. PCI to PPC Address Decoding
    59
    
    Figure 2-5. PCI to PPC Address Translation
    60
    
    PCI Slave
    61
    
    Table 2-7. PCI Slave Response Command Types
    62
    
    Pci Fifo
    65
    
    PCI Master
    65
    
    Table 2-8. PCI Master Command Codes
    66
    
    Generating PCI Cycles
    68
    
    Figure 2-6. PCI Spread I/O Address Translation
    70
    
    PCI Arbiter
    73
    
    Table 2-9. PCI Arbiter Pin Description
    73
    
    Table 2-10. Fixed Mode Priority Level Setting
    74
    
    Table 2-11. Mixed Mode Priority Level Setting
    75
    
    Table 2-12. Arbitration Setting
    76
  - Endian Conversion
    77
    
    When PPC Devices Are Big-Endian
    77
    
    When PPC Devices Are Little Endian
    78
    
    Figure 2-7. Big-To-Little-Endian Data Swap
    78
    
    PHB Registers
    79
    
    Table 2-13. Address Modification for Little-Endian Transfers
    79
  - Error Handling
    80
  - Watchdog Timers
    81
  - PCI/PPC Contention Handling
    83
  - Table 2-14. Wdtxcntl Programming
    83
  - Transaction Ordering
    86
  - PHB Hardware Configuration
    88
  - Table 2-15. PHB Hardware Configuration
    88
- Multi-Processor Interrupt Controller (MPIC)
  89
  - MPIC Features
    89
  - Architecture
    90
  - External Interrupt Interface
    90
  - Figure 2-8. Serial Mode Interrupt Scan
    90
  - Csr's Readability
    91
  - Interrupt Source Priority
    91
  - Processor's Current Task Priority
    92
  - Nesting of Interrupt Events
    92
  - Spurious Vector Generation
    92
  - Interprocessor Interrupts (IPI)
    93
  - 8259 Compatibility
    93
  - Hawk Internal Errror Interrupt
    93
  - Timers
    94
  - Interrupt Delivery Modes
    94
  - Block Diagram Description
    95
    
    Program Visible Registers
    96
    
    Figure 2-9. MPIC Block Diagram
    96
    
    Interrupt Pending Register (IPR)
    97
    
    Interrupt Selector (IS)
    97
    
    Interrupt Request Register (IRR)
    98
    
    In-Service Register (ISR)
    98
    
    Interrupt Router
    98
  - Programming Notes
    100
    
    External Interrupt Service
    100
    
    Reset State
    101
  - Operation
    102
    
    Interprocessor Interrupts
    102
    
    Dynamically Changing I/O Interrupt Configuration
    102
    
    EOI Register
    103
    
    Interrupt Acknowledge Register
    103
    
    8259 Mode
    103
    
    Current Task Priority Level
    103
  - Architectural Notes
    104
  - Effects of Interrupt Serialization
    104
- Registers
  105
  - PPC Registers
    106
    
    Table 2-16. PPC Register Map for PHB
    106
    
    Revision ID Register
    108
    
    Vendor ID/Device ID Registers
    108
    
    General Control-Status/Feature Registers
    109
    
    PPC Arbiter/Pci Arbiter Control Registers
    111
    
    Hardware Control-Status/Prescaler Adjust Register
    115
    
    PPC Error Test/Error Enable Register
    117
    
    PPC Error Status Register
    120
    
    PPC Error Address Register
    122
    
    PPC Error Attribute Register
    123
    
    PCI Interrupt Acknowledge Register
    125
    
    PPC Slave Address (0,1 and 2) Registers
    126
    
    PPC Slave Offset/Attribute (0, 1 and 2) Registers
    127
    
    PPC Slave Address (3) Register
    128
    
    PPC Slave Offset/Attribute (3) Registers
    129
    
    Wdtxcntl Registers
    130
    
    General Purpose Registers
    133
    
    Wdtxstat Registers
    133
- PCI Registers
  134
  - Table 2-17. PCI Configuration Register
    134
  - Table 2-18. PCI I/O Register
    135
  - Vendor ID/ Device ID Registers
    135
  - PCI Command/ Status Registers
    136
  - Header Type Register
    138
  - Revision ID/ Class Code Registers
    138
  - MPIC I/O Base Address Register
    139
  - MPIC Memory Base Address Register
    139
  - PCI Slave Address (0,1,2, and 3) Registers
    140
  - PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
    141
  - CONFIG_ADDRESS Register
    143
  - CONFIG_DATA Register
    146
- MPIC Registers
  147
  - Feature Reporting Register 0
    147
  - Global Configuration Register 0
    147
  - Table 2-19. MPIC Register Map
    148
  - Table 2-20. Cascade Mode Encoding
    152
  - Table 2-21. Tie Mode Encoding
    152
  - Vendor Identification Register
    153
  - Processor Init Register
    153
  - IPI Vector/Priority Registers
    154
  - Spurious Vector Register
    155
  - Timer Frequency Register
    155
  - Timer Current Count Registers
    156
  - Timer Basecount Registers
    157
  - Timer Vector/Priority Registers
    158
  - Timer Destination Registers
    159
  - External Source Vector/Priority Registers
    159
  - External Source Destination Registers
    161
  - Hawk Internal Error Interrupt Vector/Priority Register
    162
  - Hawk Internal Error Interrupt Destination Register
    163
  - Interprocessor Interrupt Dispatch Registers
    163
  - Current Task Priority Registers
    164
  - Interrupt Acknowledge Registers
    164
  - End-Of-Interrupt Registers
    165
CHAPTER 3 System Memory Controller (SMC)

166
- Introduction
  166
  - Overview
    166
  - Bit Ordering Convention
    166
  - Features
    166
- Block Diagrams
  167
- Figure 3-1. Hawk Used with Synchronous DRAM in a System
  167
- Figure 3-2. Hawk's System Memory Controller Internal Data Paths
  168
- Figure 3-3. Overall SDRAM Connections
  169
- Figure 3-4. Hawk's System Memory Controller Block Diagram
  170
- Functional Description
  171
  - SDRAM Accesses
    171
    
    Four-Beat Reads/Writes
    171
    
    Single-Beat Reads/Writes
    171
    
    Address Pipelining
    171
    
    Page Holding
    172
    
    SDRAM Speeds
    172
    
    Table 3-1. 60X Bus to SDRAM Estimated Access Timing at 100 Mhz
    172
  - SDRAM Organization
    174
  - Ppc60X Bus Interface
    174
    
    Responding to Address Transfers
    174
    
    Completing Data Transfers
    174
    
    Ppc60X Data Parity
    175
    
    Ppc60X Address Parity
    175
    
    Cache Coherency
    176
    
    Cache Coherency Restrictions
    176
    
    L2 Cache Support
    176
  - Sdram Ecc
    176
    
    Cycle Types
    176
    
    Error Reporting
    177
    
    Table 3-2. Error Reporting
    177
    
    Error Logging
    178
  - Rom/Flash Interface
    179
    
    Table 3-3. Ppc60X to Rom/Flash (16 Bit Width)
    181
    
    Table 3-4. Ppc60X to Rom/Flash (64 Bit Width) Address Mapping (Continued)
    182
    
    Rom/Flash Speeds
    184
    
    Table 3-5. Ppc60X Bus to Rom/Flash Access Timing (120Ns @ 100 Mhz)
    184
    
    Table 3-6. Ppc60X Bus to Rom/Flash Access Timing (80Ns @ 100 Mhz)
    185
    
    Table 3-7. Ppc60X Bus to Rom/Flash Access Timing (50Ns @ 100 Mhz)
    185
    
    Table 3-8. Ppc60X Bus to Rom/Flash Access Timing (30Ns @ 100 Mhz)
    186
  - I2C Interface
    187
    
    I2C Byte Write
    188
    
    Figure 3-5. Programming Sequence for I 2 C Byte Write
    189
    
    I2C Random Read
    190
    
    I2C Current Address Read
    192
    
    I2C
    194
    
    I2C Sequential Read
    196
  - Refresh/Scrub
    199
  - CSR Accesses
    199
  - External Register Set
    199
  - Chip Configuration
    200
- Programming Model
  200
  - CSR Architecture
    200
  - Register Summary
    201
  - Table 3-9. Register Summary
    201
  - Detailed Register Bit Descriptions
    203
    
    Vendor/Device Register
    204
    
    Revision ID/General Control Register
    204
    
    SDRAM Enable and Size Register (Blocks A, B, C, D)
    206
    
    Table 3-10. Block_A/B/C/D/E/F/G/H Configurations
    207
    
    SDRAM Base Address Register (Blocks A/B/C/D)
    208
    
    CLK Frequency Register
    209
    
    ECC Control Register
    210
    
    Figure 3-10. Read/Write Check-Bit Data Paths
    211
    
    Error Logger Register
    214
    
    Error_Address Register
    216
    
    Scrub/Refresh Register
    216
    
    Scrub Address Register
    217
    
    ROM a Base/Size Register
    218
    
    Table 3-11. ROM Block a Size Encoding
    219
    
    Table 3-13. Read/Write to Rom/Flash
    220
    
    ROM B Base/Size Register
    221
    
    Table 3-14. ROM Block B Size Encoding
    222
    
    ROM Speed Attributes Registers
    223
    
    Table 3-15. ROM Speed Bit Encodings
    224
    
    Data Parity Error Log Register
    225
    
    Data Parity Error Address Register
    226
    
    Data Parity Error Upper Data Register
    226
    
    Data Parity Error Lower Data Register
    227
    
    I2C Clock Prescaler Register
    228
    
    I2C Transmitter Data Register
    230
    
    I2C Receiver Data Register
    231
    
    SDRAM Enable and Size Register (Blocks E,F,G,H)
    231
    
    SDRAM Base Address Register (Blocks E/F/G/H)
    232
    
    SDRAM Speed Attributes Register
    233
    
    Table 3-16. Trc Encoding
    234
    
    Table 3-17. tras Encoding
    234
    
    Address Parity Error Log Register
    235
    
    Address Parity Error Address Register
    236
    
    32-Bit Counter
    237
    
    External Register Set
    237
    
    Tben Register
    238
- Software Considerations
  239
- ECC Codes
  251
- Table 3-21. Syndrome Codes Ordered by Bit in Error
  251
- Table 3-22. Single Bit Errors Ordered by Syndrome Code
  252

Motorola MVME5100 Series Manual (127 pages)

Single Board Computer

Brand: Motorola | Category: Desktop | Size: 2.24 MB

Table of Contents
7
About this Manual

15
- Summary of Changes
  17
- Overview of Contents
  17
- Comments and Suggestions
  18
- Conventions Used in this Manual
  19
  - Terminology
    19
1 Hardware Preparation and Installation

21
2 Operation

33
- Introduction
  33
- Switches and Indicators
  33
  - ABT/RST Switch
    33
    
    Abort Function
    33
    
    Reset Function
    33
  - Status Indicators
    34
    
    CPU Indicator (DS2)
    34
    
    RST Indicator (DS1)
    34
  - Connectors
    34
    
    10/100 BASE T Ports
    34
    
    DEBUG Port
    34
- System Powerup
  35
  - Initialization Process
    35
  - Figure 2-1. Boot-Up Sequence
    35
3 Ppcbug Firmware

37
- Introduction
  37
- Ppcbug Overview
  37
  - Implementation and Memory Requirements
    38
- Using Ppcbug
  38
  - Hardware and Firmware Initialization
    39
- Default Settings
  40
- Standard Commands
  51
  - Table 3-1. Debugger Commands
    51
  - Diagnostics
    55
  - Table 3-2. Diagnostic Test Groups
    55
4 Functional Description

57
- Introduction
  57
- Features Summary
  57
- Table 4-1. MVME5100 General Features
  57
- Features Descriptions
  58
  - General
    58
  - Processor
    59
  - Figure 4-1. MVME5100 Block Diagram
    59
  - System Memory Controller and PCI Host Bridge
    60
  - Memory
    60
    
    Flash Memory
    60
    
    ECC SDRAM Memory
    61
  - P2 Input/Output (I/O) Modes
    61
  - Input/Output Interfaces
    61
    
    Ethernet Interface
    61
    
    Asynchronous Communications
    62
    
    IDSEL Routing
    62
    
    Interrupt Routing
    62
    
    Real-Time Clock & NVRAM & Watchdog Timer
    62
    
    Timers
    62
    
    Vmebus Interface
    62
5 RAM500 Memory Expansion Module

63
6 Pin Assignments

73
7 Programming the MVME5100

93
- Introduction
  93
- Memory Maps
  93
- Programming Considerations
  97
  - PCI Arbitration
    97
  - Figure 7-1. Vmebus Master Mapping
    98
  - Table 7-4. PCI Arbitration Assignments
    98
  - Interrupt Handling
    99
  - DMA Channels
    100
  - Figure 7-2. MVME5100 Interrupt Architecture
    100
  - Sources of Reset
    101
  - Table 7-5. Devices Affected by Various Resets
    101
  - Endian Issues
    102
    
    PCI and Ethernet
    102
    
    PCI Domain
    102
    
    Processor/Memory Domain
    102
    
    Role of the Hawk ASIC
    102
    
    Role of the Universe ASIC
    102
    
    Vmebus Domain
    103
Specifications

105
- General Specifications
  105
- Table A-1. MVME5100 Specifications
  105
- Power Requirements
  106
- Cooling Requirements
  106
- EMC Compliance
  106
- Table A-2. Power Consumption
  106
Troubleshooting

107
- Solving Startup Problems
  107
- Table B-1. Troubleshooting Problems
  107

Motorola MVME5100 Series Installation & Use Manual (107 pages)

Brand: Motorola | Category: Single board computers | Size: 1.33 MB

Motorola MVME5100 Series Specification Sheet (5 pages)

Motorola VME Processor Modules Specification Sheet

Brand: Motorola | Category: Computer Hardware | Size: 0.3 MB

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