Page 1 MVME5100 Single Board Computer Programmer’s Reference Guide V5100A/PG1 November 2000 Edition...
Page 2 © Copyright 2000 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola and the Motorola logo are registered trademarks and AltiVec is a trademark of Motorola, Inc. PowerPC and the PowerPC logo are registered trademarks; and PowerPC 750 is a trademark of International Business Machines Corporation and are used by Motorola, Inc.
Page 3 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
Page 4 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
Page 5 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Page 6 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013...
Page 7 MPC750. As of the printing date of this manual, the MVME5100 is available in the configurations shown below. All models of the MVME5100 are available with either VME SCANBE front panel (-01x1) or IEEE 1101 compatible front panel (-01x3).
Page 8 Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can improve them. Mail comments to: Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way...
Page 9 Terminology A character precedes a data or address parameter to specify the numeric format, as follows (if not specified, the format is hexadecimal): Specifies a hexadecimal number Specifies a binary number & Specifies a decimal number An asterisk (#) following a signal name for signals that are level significant denotes that the signal is true or valid when the signal is low.
Page 10: Table Of Contents
The Universe ASIC.....................1-8 PCI Configuration Space ..................1-8 PCI Arbitration Assignments for Hawk ASIC ..........1-10 Hawk External Register Bus Address Assignments .........1-11 MVME5100 Hawk External Register Bus Summary........1-11 Status Register ....................1-13 MODFAIL Bit Register ..................1-14 MODRST Bit Register..................1-15 TBEN Bit Register....................1-16 NVRAM/RTC &...
Page 11 CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Introduction ....................... 2-1 Overview ......................2-1 Features ......................2-1 Block Diagram......................2-3 Functional Description ....................2-4 Architectural Overview ..................2-4 PPC Bus Interface ....................2-5 PPC Address Mapping ................2-6 PPC Slave....................
Page 12 8259 Compatibility ...................2-54 Hawk Internal Errror Interrupt................2-54 Timers .......................2-55 Interrupt Delivery Modes..................2-55 Block Diagram Description ................2-56 Program Visible Registers .................2-58 Interrupt Pending Register (IPR)...............2-58 Interrupt Selector (IS)................2-58 Interrupt Request Register (IRR)...............2-59 In-Service Register (ISR) ................2-59 Interrupt Router ..................2-59 Programming Notes ..................2-61 External Interrupt Service................2-61 Reset State ....................2-62 Operation ......................2-63...
Page 13 PCI Registers ....................2-95 Vendor ID/ Device ID Registers ............... 2-96 PCI Command/ Status Registers ............... 2-97 Revision ID/ Class Code Registers ............2-99 Header Type Register................2-99 MPIC I/O Base Address Register ............2-100 MPIC Memory Base Address Register ........... 2-100 PCI Slave Address (0,1,2, and 3) Registers ..........
Page 14 CHAPTER 3 System Memory Controller (SMC) Introduction........................3-1 Overview......................3-1 Bit Ordering Convention ..................3-1 Features.......................3-1 Block Diagrams ......................3-2 Functional Description....................3-6 SDRAM Accesses....................3-6 Four-beat Reads/Writes ................3-6 Single-beat Reads/Writes ................3-6 Address Pipelining..................3-6 Page Holding ....................3-7 SDRAM Speeds...................3-7 SDRAM Organization ..................3-9 PPC60x Bus Interface..................3-9 Responding to Address Transfers..............3-9 Completing Data Transfers................3-9 PPC60x Data Parity ...................3-10 PPC60x Address Parity ................3-10...
Page 15 Detailed Register Bit Descriptions ..............3-38 Vendor/Device Register ................3-39 Revision ID/General Control Register ............3-39 SDRAM Enable and Size Register (Blocks A, B, C, D)......3-41 SDRAM Base Address Register (Blocks A/B/C/D) ......... 3-43 CLK Frequency Register................3-44 ECC Control Register ................3-45 Error Logger Register ................
Page 16 8259 Interrupts....................4-2 Exceptions........................4-4 Sources of Reset....................4-4 Soft Reset......................4-4 CPU Reset......................4-4 Error Notification and Handling .................4-5 Endian Issues ......................4-6 Processor/Memory Domain ................4-8 MPIC’s Involvement...................4-8 PCI Domain ......................4-8 APPENDIX A Related Documentation Motorola Computer Group Documents ..............A-1 Manufacturers’ Documents..................A-2 Related Specifications....................A-3 xvii...
Page 17 List of Figures Figure 1-1. MVME5100 Block Diagram ..............1-3 Figure 2-1. Hawk PCI Host Bridge Block Diagram ..........2-3 Figure 2-2. PPC to PCI Address Decoding..............2-6 Figure 2-3. PPC to PCI Address Translation .............2-7 Figure 2-4. PCI to PPC Address Decoding..............2-20 Figure 2-5.
Page 18 Table 1-3. On-Board PCI Device Identification ............1-9 Table 1-4. PCI Arbitration Assignments for Hawk ASIC ........1-10 Table 1-5. Hawk External Register Bus Summary ..........1-11 Table 1-6. MVME5100 Status Register ..............1-13 Table 1-7. MODFAIL Bit Register ................1-14 Table 1-8. MODRST Bit Register................1-15 Table 1-9.
Page 19 Table 4-1. MPIC Interrupt Assignments..............4-1 Table 4-2. PBC ISA Interrupt Assignments .............. 4-3 Table 4-3. Error Notification and Handling............... 4-5 Table A-1. Motorola Computer Group Documents ..........A-1 Table A-2. Manufacturers’ Documents ..............A-2 Table A-3. Related Specifications ................A-3...
Page 20: Introduction
What this Guide Provides This guide provides programming information and other data applicable to the MVME5100. As an added convienience, it also provides details of the chip set (Hawk) programming functions. It is important to note that much of the board’s programming functionality is associated with the Hawk ASIC.
Page 21: Table 1-1. Mvme Key Features
Product Data and Memory Maps The following table lists the key features of the MVME5100. Table 1-1. MVME Key Features Feature Specification Microprocessors and • MPC7400 @400 MHz Internal Clock Frequency Bus Clock Frequency • MPC750 @450 MHz Internal Clock Frequency •...
Page 22: Figure 1-1. Mvme5100 Block Diagram
PCI Host Bridge (PHB) RTC/NVRAM/WD M48T37V Hawk X-bus 33 MHz 32/64-bit PCI Local Bus TL16C550 UART VME Bridge Ethernet 1 Ethernet 2 Universe 2 10/100TX 10/100TX Buffers 761 or PMC VME P2 VME P1 Figure 1-1. MVME5100 Block Diagram http://www.motorola.com/computer/literature...
Page 23: Memory Maps
Specification listed in Appendix A, Related Documentation. The MVME5100 is fully capable of supporting both the PREP and the CHRP processor memory maps with ROM/FLASH size limited to 16MBytes and RAM size limited to 1GB. PCI / VME Memory Map Following a reset, the Hawk ASIC disables all PCI slave map decoders.
Page 24: Processor Pll Configuration
L2 Cache The MVME5100 incorporates an L2 cache using a 2-way, set-associative tag memory located in the MPC7400 processor, with external direct- mapped synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated L2 cache port on the processor.
Page 25: System Memory
E (second mezzanine attached). Serial Presence Detect (SPD) Definitions The MVME5100 SPD uses the SPD JEDEC standard definition. On board SPD for SDRAM Bank A or both A and B of the Hawk shall be accessed at Address $A8 . Only Bank A or Banks A and B will be populated. If both banks A and B are populated, they will be the same speed and memory size.
Page 26: Vital Product Data And Serial Presence Detect Data
There can be seven slave devices connected to the I C bus on the MVME5100. The Vital Product Data (VPD) address shall be $A0. The User configuration Data (UPD) address shall be $A2. The on-board MSD address (Memory Bank A and B) shall be $A8. The optional Memory Mezzanine 1 MSD addresses shall be $AA (Memory Bank C) and $AC (Memory Bank E) for mezzanine 2.
Page 27: The Ethernet Controller
Up to two PMC slots and one PCIX slot may be present. The presence of the PMC’s and/or PCIX can be positively determined by reading the Base Module Feature Register. The INTA#, INTB#, INTC#, and INTD# from the three PMC/PCIX slots are routed by MVME5100 as follows: PMC Slot 1 PMC Slot 2...
Page 28: Table 1-2. Idsel Mapping For Pci Devices
PCI Expansion (PMCSPAN) Note: AD20 connection to IDSEL is made on the PMCSPAN The following table shows the Vendor ID, the Device ID, and Revision ID for each of the on-board PCI devices on MVME5100: Table 1-3. On-Board PCI Device Identification Device...
Page 29: Pci Arbitration Assignments For Hawk Asic
The PCI arbitration is performed by the Hawk ASIC which supports eight external PCI masters. This includes Hawk and 7 external PCI masters. The arbitration assignments on MVME5100 are as follows: Table 1-4. PCI Arbitration Assignments for Hawk ASIC PCI BUS REQUEST...
Page 30: Hawk External Register Bus Address Assignments
Address Assignments on MVME5100. The address range for the External Register Set on MVME5100 is fixed at $FEF88000-$FEF8FFFF. MVME5100 Hawk External Register Bus Summary The Hawk External Register Summary of the MVME5100 is shown in the table below: Table 1-5. Hawk External Register Bus Summary...
Page 31 Product Data and Memory Maps Table 1-5. Hawk External Register Bus Summary (Continued) Bits: REQUIRED (r) Address OPTIONAL (o) Register Name by PowerPlus II 0 1 2 3 4 5 6 7 $FEF880C8 NVRAM/RTC ADDR THIS GROUP $FEF880D0 NVRAM/RTC ADDR OPTIONAL $FEF880D8 NVRAM/RTC DATA...
Page 32: Status Register
Hawk ASIC Status Register The MVME5100 implementation of this Register is fully compliant with the description provided within the PowerPlus II programming with the following exceptions: An 8-bit status register, accessible through the External Register Set port, which defines the status of the Module.
Page 33: Modfail Bit Register
Product Data and Memory Maps MODFAIL Bit Register The MVME5100 implementation of this Register is fully compliant with the PowerPlus PowerPlus IIII programming with the following exceptions: The MODFAIL Bit Register provides the means to illuminate the module Fail LED.
Page 34: Modrst Bit Register
This bit is undefined when reading. RESET_REQ Clearing this bit causes the RST_REQ_ signal to be asserted. This bit will automatically deassert following reset. The host board is expected to assert a PCI reset when this signal is cleared. http://www.motorola.com/computer/literature 1-15...
Page 35: Tben Bit Register
The MVME5100’s NVRAM/RTC and Watchdog Timer functions are fully compliant with the PowerPlus II internal programming configuration. Software Readable Header Register The MVME5100’s use of this Register is fully compliant with the PowerPlus II internal programming configuration. 1-16 Computer Group Literature Center Web Site...
Page 36: Geographical Address Register (Vme Board)
Hawk ASIC Geographical Address Register (VME board) The MVME5100’s use of this Register is fully compliant with the PowerPlus II internal programming configuration. Extended Features Register 1 This register is used to read if a PMC board is present or if a PCI expansion slot is present.
Page 37: Extended Features Register 2
Product Data and Memory Maps Extended Features Register 2 This register is used to read if a PMC board is present or if a PCI expansion slot is present. Table 1-11. Extended Features Register 2 Extended Features Register 2 - Offset 80F0h FIELD OPER RESET...
Page 38: Interrupt Handling
The interrupt architecture for the MVME5100 is fully compliant with the PowerPlus II internal programming configuration. The following sections further describe MVME5100 interrupt related issues. Hawk MPIC The Hawk MPIC interrupt assignment for the MVME5100 is shown in the following table: Table 1-12. Hawk MPIC Interrupt Assignments MPIC...
Page 39 Product Data and Memory Maps Notes 1. Interrupting device is addressed from Hawk External Register Bus. 2. The mapping of interrupt sources from the VMEbus and Universe internal interrupt sources are programmable via the Local Interrupt Map 0 Register and the Local Interrupt Map 1 Register in the Universe ASIC.
Page 40: Introduction
2Hawk PCI Host Bridge & Multi- Processor Interrupt Controller Introduction Overview This chapter describes the architecture and usage of the PowerPC to PCI Local Bus Bridge (PHB) and the Multi-Processor Interrupt Controller (MPIC) portion of the Hawk ASIC. The Hawk is intended to provide PowerPC 60x (PPC60x) compliant devices access to devices residing on the PCI Local Bus.
Page 41 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller – Read-ahead buffer for reads from the PPC bus. – Four independent software programmable slave map decoders. Interrupt Controller – MPIC compliant. – MPIC programming model. – Support for 16 external interrupt sources and two processors. –...
Page 42: Block Diagram
Block Diagram Block Diagram Figure 2-1. Hawk PCI Host Bridge Block Diagram http://www.motorola.com/computer/literature...
Page 43: Functional Description
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Functional Description Architectural Overview A functional block diagram of the Hawk’s PHB is shown in Figure 2-1. The PHB control logic is subdivided into the following functions: PCI slave, PCI master, PPC slave and PPC master. The PHB data path logic is subdivided into the following functions: PCI FIFO, PPC FIFO, PCI Input, PPC Input, PCI Output, and PPC Output.
Page 44: Ppc Bus Interface
PCI Parity block. PPC Bus Interface The PPC Bus Interface connects directly to one MPC750 or MPC7400 microprocessor and one peripheral PPC60x master device. It uses a subset of the capabilities of the PPC bus protocol. http://www.motorola.com/computer/literature...
Page 45: Ppc Address Mapping
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Address Mapping The PHB will map either PCI memory space or PCI I/O space into PPC address space using four programmable map decoders. These decoders provide windows into the PCI bus from the PPC bus. The most significant 16 bits of the PPC address are compared with the address range of each map decoder, and if the address falls within the specified range, the access is passed on to the PCI.
Page 46: Ppc Slave
PPC Slave will hold off asserting AACK_ and TA_ until after the transaction has completed on the PCI bus. This has the effect of removing all levels of pipelining during compelled PHB accesses. The interdependency between the assertion of http://www.motorola.com/computer/literature...
Page 47: Table 2-1. Ppc Slave Response Command Types
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller AACK_ and TA_ allows the PPC Slave to assert a retry to the processor in the event that the transaction is unable to complete on the PCI side. It should be noted that any transaction that crosses a PCI word boundary could be disrupted after only having a portion of the data transferred.
Page 48: Ppc Fifo
PPC Slave and the PCI Master. If write posting has been enabled, then the maximum number of transactions that may be posted is limited by the abilities of either the data FIFO or the command FIFO. http://www.motorola.com/computer/literature...
Page 49: Ppc Master
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller For example, two burst transactions would make the data FIFO the limiting factor for write posting. Four single beat transactions would make the command FIFO be the limiting factor. If either limit is exceeded, then any pending PPC transactions will be delayed (AACK_ and TA_ will not be asserted) until the PCI Master has completed a portion of the previously posted transactions and created some room within the command and/or...
Page 50: Table 2-2. Ppc Master Transaction Profiles And Starting Offsets
PCI Slave is continuously stalling during write posted transactions, then further tuning might be needed. This can be accomplished by changing the WXFT (Write Any Fifo Threshold) field within the PSATTx registers to recharacterize PHB write posting mechanism. The FIFO http://www.motorola.com/computer/literature 2-11...
Page 51: Table 2-3. Ppc Master Write Posting Options
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller threshold should be lowered to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus. Table 2-3 summarizes the PHB available write posting options. Table 2-3. PPC Master Write Posting Options WPEN PPC60x Start PPC60x Continuation...
Page 52 GBL bit determines whether or not the GBL_ signal is asserted for all portions of a transaction and is fully independent of the PCI command code and INV bit. The following table shows the relationship between the PCI command codes and the INV bit. http://www.motorola.com/computer/literature 2-13...
Page 53: Table 2-5. Ppc Master Transfer Types
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-5. PPC Master Transfer Types PCI Command Code PPC Transfer Type PPC Transfer Size TT0-TT4 Memory Read Read Burst/Single Beat 01010 Memory Read Multiple Memory Read Line Memory Read Read With Intent to Burst/Single Beat 01110 Modify...
Page 54: Ppc Arbiter
Output CPU1 Grant_ Input CPU1 Grant_ XARB2 BiDir Tristate Output EXTL Grant_ Input EXTL Grant_ XARB3 BiDir Tristate Input CPU0 Request_ Output HAWK Request_ XARB4 Input Input CPU1 Request_ Input HAWK Grant_ XARB5 Input Input EXTL Request_ Input http://www.motorola.com/computer/literature 2-15...
Page 55 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller While RST_ is asserted, XARB0 through XARB4 will be held in tri-state. If the internal arbiter mode is selected, then XARB0 through XARB3 will be driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST_.
Page 56: Ppc Parity
Address parity errors can only be injected during cycles where PHB is sourcing a PPC address. PHB does not have the ability to check for address parity errors. http://www.motorola.com/computer/literature 2-17...
Page 57: Ppc Bus Timer
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Bus Timer The PPC Timer allows the current bus master to recover from a potential lock-up condition caused when there is no response to a transfer request. The time-out length of the bus timer is determined by the XBT field within the GCSR.
Page 58: Pci Bus Interface
PPC bus. An example of this is shown in Figure 2-4. http://www.motorola.com/computer/literature 2-19...
Page 59: Figure 2-4. Pci To Ppc Address Decoding
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI Bus Address 8 0 8 0 1 2 3 4 Decode is >= <= PSADDx Register 7 0 8 0 9 0 0 0 Figure 2-4. PCI to PPC Address Decoding There are no limits imposed by the PHB on how large of an address space a map decoder can represent.
Page 60: Figure 2-5. Pci To Ppc Address Translation
The decoders are prioritized as shown below. Decoder Priority PCI Slave 0 highest PCI Slave 1 PCI Slave 2 PCI Slave 3 lowest http://www.motorola.com/computer/literature 2-21...
Page 61: Pci Slave
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC Control Registers The MPIC control registers are located within either PCI Memory or PCI I/O space using traditional PCI defined base registers within the predefined 64-byte header. Refer to the section titled Multi-Processor Interrupt Controller (MPIC) for more information.
Page 62: Table 2-7. Pci Slave Response Command Types
PCI Slave returns an entire word of data regardless of the byte enables. During I/O read cycles, the PCI Slave performs integrity checking of the byte enables against the address being presented and assert SERR* in the event there is an error. http://www.motorola.com/computer/literature 2-23...
Page 63 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave only honors the Linear Incrementing addressing mode. The PCI Slave performs a disconnect with data if any other mode of addressing is attempted. Device Selection The PCI slave will always respond valid decoded cycles as a medium responder.
Page 64 PHB results in the PCI Slave issuing a retry. Parity The PCI Slave supports address parity error detection, data parity generation, and data parity error detection. Cache Support The PCI Slave does not participate in the PCI caching protocol. http://www.motorola.com/computer/literature 2-25...
Page 65: Pci Fifo
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI FIFO A 64-bit by 16 entry FIFO (4 cache lines total) is used to hold data between the PCI Slave and the PPC Master to ensure that optimum data throughput is maintained. The same FIFO is used for both read and write transactions. A 52-bit by 4 entry FIFO is used to hold command information being passed between the PCI Slave and the PPC Master.
Page 66: Table 2-8. Pci Master Command Codes
PPC Mapped PCI Space Read 0110 Memory Read Write 0111 Memory Write -- Unsupported -- 1000 Reserved -- Unsupported -- 1001 Reserved CONADD/CONDAT Read 1010 Configuration Read CONADD/CONDAT Write 1011 Configuration Write -- Unsupported -- 1100 Memory Read Multiple http://www.motorola.com/computer/literature 2-27...
Page 67 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-8. PCI Master Command Codes (Continued) Entity Addressed TBST* C/BE PCI Command Transfer Type -- Unsupported -- 1101 Dual Address Cycle PPC Mapped PCI Space Read 1110 Memory Read Line -- Unsupported -- 1111 Memory Write and Invalidate...
Page 68: Generating Pci Cycles
The PCI Master does not participate in the PCI caching protocol. Generating PCI Cycles There are four basic types of bus cycles that can be generated on the PCI bus: Memory and I/O Configuration Special Cycle Interrupt Acknowledge http://www.motorola.com/computer/literature 2-29...
Page 69 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Memory and I/O Cycles Each programmable slave may be configured to generate PCI I/O or memory accesses through the MEM and IOM fields in its XSATTx register as shown below. PCI Cycle Type Memory Contiguous I/O...
Page 70: Figure 2-6. Pci Spread I/O Address Translation
Performing a configuration access is a two step process. The first step is to place the address of the configuration cycle within the CONFIG_ADDRESS register. Note that this action does not generate any cycles on the PCI bus. http://www.motorola.com/computer/literature 2-31...
Page 71 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The second step is to either read or write configuration data into the CONFIG_DATA register. If the CONFIG_ADDRESS register is set up correctly, the PHB will pass this access on to the PCI bus as a configuration cycle.
Page 72 After the write to CONFIG_ADDRESS has been accomplished, the next write to the CONFIG_DATA register causes the PHB to generate a special cycle on the PCI bus. The write data is driven onto AD[31:0] during the special cycle’s data phase. http://www.motorola.com/computer/literature 2-33...
Page 73: Pci Arbiter
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Interrupt Acknowledge Cycles Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge cycle. Any single byte or combination of bytes may be read from, and the actual byte enable pattern used during the read will be passed on to the PCI bus.
Page 74: Table 2-10. Fixed Mode Priority Level Setting
Notes 1. “000” is the default setting in fixed mode. 2. The HEIR setting only covers a small subset of all possible combinations. It is the responsibility of the system designer to connect the request/grant pair in a manner most beneficial to their design goals. http://www.motorola.com/computer/literature 2-35...
Page 75: Table 2-11. Mixed Mode Priority Level Setting
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When the arbiter is programmed for round robin priority mode, the arbiter maintains fairness and provides equal opportunity to the requestors by rotating its grants. The contents in “HEIR” field are “don’t cares” when operated in this mode.
Page 76: Table 2-12. Arbitration Setting
Park on last requestor 0001 Park on PARB6 0010 Park on PARB5 0011 Park on PARB4 0100 Park on PARB3 0101 Park on PARB2 0110 Park on PARB1 0111 Park on PARB0 1000 Park on HAWK 1111 Parking disabled http://www.motorola.com/computer/literature 2-37...
Page 77: Endian Conversion
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Notes 1. “1000” is the default setting. 2. Parking disabled is a test mode only and should not be used, since no one will drive the PCI bus when in an idle state.
Page 78: When Ppc Devices Are Little Endian
Figure 2-7. Big-to-Little-Endian Data Swap When PPC Devices are Little Endian When all PPC devices are operating in Little-Endian mode, the originating address is modified to remove the exclusive-ORing applied by PPC60x processors. Note that no data swapping is performed. http://www.motorola.com/computer/literature 2-39...
Page 79: Phb Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Address modification happens to the originating address regardless of whether the transaction originates from the PCI bus or the PPC bus. The three low order address bits are exclusive-ORed with a three-bit value that depends on the length of the operand, as shown in Table 2-13.
Page 80: Error Handling
Each bit in the ESTAT may be cleared by writing a 1 to it; writing a 0 to it has no effect. New error bits may be set only when all previous error bits have been cleared. http://www.motorola.com/computer/literature 2-41...
Page 81: Watchdog Timers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When any bit in the ESTAT is set, the PHB will attempt to latch as much information as possible about the error in the PPC Error Address (EADDR) and Attribute Registers (EATTR). Information is saved as follows: Error Error Address and...
Page 82 WDTxCNTL register. The KEY field byte lane must be selected and must be written with PATTERN_2 for the write to take affect. The effects on the WDTxCNTL register depend on the byte lanes that are written to during step 2 and are shown in Table 2-14. http://www.motorola.com/computer/literature 2-43...
Page 83: Pci/Ppc Contention Handling
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-14. WDTxCNTL Programming Byte Lane Selection Results ENAB RELOAD WDTxCNTL Register /RES 8:15 16:23 24:31 Prescaler/ Counter RES/ENAB RELOAD Enable No Change No Change No Change No Change Update Update No Change No Change from from...
Page 84 PPC FIFO. There are some performance issues related to bridge lock resolution. PHB offers two mechanism that allow fine tuning of the bridge lock resolution function. http://www.motorola.com/computer/literature 2-45...
Page 85 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Programmable Lock Resolution Consider the scenario where the PPC Slave is hosting a read cycle and the PCI Slave is hosting a posted write transaction. If both transactions happen at roughly the same time, then the PPC Slave will hold off its transaction until the PCI Slave can fill the PCI FIFO with write posted data.
Page 86: Transaction Ordering
For the same reason all PPC60x write posted transfers will also be completed before any access to the PHB PPC registers begins. The PCI Local Bus Specification 2.1 states that posted write buffers in both directions must be flushed before completing a read in either direction. http://www.motorola.com/computer/literature 2-47...
Page 87 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PHB supports this by providing two optional FIFO flushing options. The XFBR (PPC60x Flush Before Read) bit within the GCSR register controls the flushing of PCI write posted data when performing PPC-originated read transactions.
Page 88: Phb Hardware Configuration
64-bit PCI Bus 32-bit PCI Bus PPC Register Base RD[5] Register Base = $FEFF0000 Register Base = $FEFE0000 MPIC Interrupt Type RD[7] Parallel Interrupts Serial Interrupts PPC Arbiter Mode RD[8] Disabled Enabled PCI Arbiter Mode RD[9] Disabled Enabled http://www.motorola.com/computer/literature 2-49...
Page 89: Multi-Processor Interrupt Controller (Mpic)
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-15. PHB Hardware Configuration (Continued) Function Sample Pin(s) Sampled Meaning State PPC:PCI Clock Ratio RD[10:12] Reserved Reserved Reserved Multi-Processor Interrupt Controller (MPIC) The MPIC is a multi-processor structured intelligent interrupt controller. MPIC Features: MPIC programming model Supports two processors...
Page 90: Architecture
SI_STA and SI_DAT pins as shown in Figure 2-8. In parallel mode, 16 external signal pins are used as interrupt inputs (interrupts 0 through 15). PCLK SI_STA SI_DAT EXT0 EXT1 EXT2 EXT13EXT14 EXT15 Figure 2-8. Serial Mode Interrupt Scan http://www.motorola.com/computer/literature 2-51...
Page 91: Csr's Readability
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Using PCLK as a reference, external logic will pulse SI_STA one clock period indicating the beginning of an interrupt scan period. On the same clock period that SI_STA is asserted, external logic will feed the state of EXT0 on the SI_DAT pin.
Page 92: Processor's Current Task Priority
INT is asserted for an interrupt source, which is masked using the mask bit, in the Vector-Priority register before the interrupt is acknowledged. http://www.motorola.com/computer/literature 2-53...
Page 93: Interprocessor Interrupts (Ipi)
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Interprocessor Interrupts (IPI) Processors 0 and 1 can generate interrupts which are targeted for the other or both processors. There are four Interprocessor Interrupts (IPI) channels. The interrupts are initiated by writing a bit in the IPI dispatch registers. If subsequent IPI’s are initiated before the first is acknowledged, only one IPI will be generated.
Page 94: Timers
EOI is received for that interrupt. The EOI cycle indicates the end of processing for the highest priority in service interrupt. http://www.motorola.com/computer/literature 2-55...
Page 95: Block Diagram Description
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller In the distributed delivery mode, the interrupt is pointed to one or more processors but it will be delivered to only one processor. Therefore, for externally sourced or I/O interrupts, multicast delivery is not supported. The interrupt is delivered to a processor when the priority of the interrupt is greater than the priority contained in the task register for that processor, when the priority of the interrupt is greater than any interrupt which is in-...
Page 96: Program Visible Registers
Multi-Processor Interrupt Controller (MPIC) Int. signals Program Visible Registers Interrupt Interrupt Selector_1 Selector_0 IRR_1 IRR_0 ISR_1 ISR_0 Interrupt Router INT 1 INT 0 Figure 2-9. MPIC Block Diagram http://www.motorola.com/computer/literature 2-57...
Page 97: Interrupt Pending Register (Ipr)
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Program Visible Registers These are the registers that software can access. They are described in detail in the MPIC Registers section. Interrupt Pending Register (IPR) The interrupt signals to MPIC are qualified and synchronized to the clock by the IPR.
Page 98: Interrupt Request Register (Irr)
IPR associated with this interrupt. One bit for each processor. Then one of these bits is delivered to each Interrupt Selector. Since this http://www.motorola.com/computer/literature 2-59...
Page 99 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller interrupt source can be multicast, each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor. If one of the following sets of conditions is true, the interrupt pin for processor 0 is driven active.
Page 100: Programming Notes
In-Service bit for the 8259 within the MPIC and allows it to recognize higher priority interrupt requests, if any, from the 8259. If none of the nested interrupt modes of the 8259 are enabled, the interrupt handler issues an EOI request to the 8259. http://www.motorola.com/computer/literature 2-61...
Page 101: Reset State
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller – The device driver interrupt service routine associated with this interrupt vector is invoked. – If the interrupt source was not the 8259, the interrupt handler issues an EOI request for this interrupt vector to the MPIC. If the interrupt source was the 8259 and any of the nested interrupt modes of the 8259 are enabled, the interrupt handler issues an EOI request to the 8259.
Page 102: Operation
Wait for the activity bit (ACT) for that source to be cleared. Make the desired changes. Unmask the source. This sequence ensures that the vector, priority, destination, and mask information remain valid until all processing of pending interrupts is complete. http://www.motorola.com/computer/literature 2-63...
Page 103: Eoi Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller EOI Register Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event. If multiple nested interrupts are in service, the EOI command terminates the interrupt service of the highest priority source.
Page 104: Architectural Notes
MPIC logic actually sees the change. Spurious interrupts can result if an EOI cycle occurs before the interrupt source is seen to be negated by MPIC logic. http://www.motorola.com/computer/literature 2-65...
Page 105: Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Registers This section provides a detailed description of all PHB registers. The section is divided into two parts: the first covers the PPC Registers and the second covers the PCI Configuration Registers. The PPC Registers are accessible only from the PPC bus using any single beat valid transfer size.
Page 106: Ppc Registers
0 1 2 3 4 5 6 7 8 9 $FEFF0000 VENID DEVID $FEFF0004 REVID $FEFF0008 GCSR $FEFF000C XARB PARB $FEFF0010 XPAD $FEFF0014 $FEFF0018 $FEFF001C $FEFF0020 ETEST EENAB $FEFF0024 ESTAT $FEFF0028 EADDR $FEFF002C EATTR $FEFF0030 PIACK $FEFF0034 $FEFF0038 $FEFF003C $FEFF0040 XSADD0 $FEFF0044 XSOFF0 XSATT0 http://www.motorola.com/computer/literature 2-67...
Page 107 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-16. PPC Register Map for PHB (Continued) Bit ---> 0 1 2 3 4 5 6 7 8 9 $FEFF0048 XSADD1 $FEFF004C XSOFF1 XSATT1 $FEFF0050 XSADD2 $FEFF0054 XSOFF2 XSATT2 $FEFF0058 XSADD3 $FEFF005C XSOFF3 XSATT3...
Page 108: Vendor Id/Device Id Registers
Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola and is hardwired as a read-only value. This register is duplicated in the PCI Configuration Registers.
Page 109: General Control-Status/Feature Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller General Control-Status/Feature Registers The General Control-Status Register (GCSR) provides miscellaneous control and status information for the PHB. The bits within the GCSR are defined as follows: Address $FEFF0008 0 1 2 3 4 5 6 7 8 9 Name GCSR Operation...
Page 110 PPC Arbiter. In a multi- processor environment, these bits allow software to determine on which processor it is currently running. Current PPC Data Bus Master device on ABG0* device on ABG1* device on ABG2 Hawk http://www.motorola.com/computer/literature 2-71...
Page 111: Ppc Arbiter/Pci Arbiter Control Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Arbiter/PCI Arbiter Control Registers The PPC Arbiter Register (XARB) provides control and status for the PPC Arbiter. Refer to the section titled PPC Arbiter for more information. The bits within the XARB register are defined as follows: Address $FEFF000C 0 1 2 3 4 5 6 7 8 9...
Page 112 PARB register are defined as follows: PRIx Priority. This field is used by the PCI Arbiter to establish a particular bus priority scheme. The encoding of this field is shown in the following table. Priority Scheme Fixed Round Robin Mixed Reserved http://www.motorola.com/computer/literature 2-73...
Page 113 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PRKx Parking. This field is used by the PCI Arbiter to establish a particular bus parking scheme. The encoding of this field is shown in the following table. Parking Scheme 0000 Park on last master 0001 Park always on PARB6 0010...
Page 114 If cleared, the PCI Arbiter is disabled and external logic is implementing the system arbiter. Please refer to the section titled PHB Hardware Configuration for more information on how this bit gets set. http://www.motorola.com/computer/literature 2-75...
Page 115: Hardware Control-Status/Prescaler Adjust Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Hardware Control-Status/Prescaler Adjust Register The Hardware Control-Status Register (HCSR) provides hardware specific control and status information for the PHB. The bits within the HCSR are defined as follows: Address $FEFF0010 Name HCSR XPAD Operation Reset...
Page 116 1MHz. The scale factor is calculated as follows: XPAD = 256 - Clk, where Clk is the frequency of the CLK input in MHz. The following table shows the scale factors for some common CLK frequencies. Frequency XPAD http://www.motorola.com/computer/literature 2-77...
Page 117: Ppc Error Test/Error Enable Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Error Test/Error Enable Register The Error Test Register (ETEST) provides you with a way to send certain types of errors to test the PHB error capture and status circuitry. The bits within the ETEST are defined as follows: Address $FEFF0020...
Page 118 Enable. When this bit is set, the PRTA bit in the ESTAT register will be used to assert the MCHK output to the bus master which initiated the transaction. When this bit is clear, MCHK will not be asserted. http://www.motorola.com/computer/literature 2-79...
Page 119 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller XBTOI PPC Address Bus Time-out Interrupt Enable. When this bit is set, the XBTO bit in the MERST register will be used to assert an interrupt through the MPIC interrupt controller. When this bit is clear, no interrupt will be asserted.
Page 120: Ppc Error Status Register
EENAB register is set, the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register. When the XDPEI bit in the EENAB register is set, the assertion of this bit will assert an interrupt through the MPIC. http://www.motorola.com/computer/literature 2-81...
Page 121 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPER PCI Parity Error. This bit is set when the PCI PERR_ pin is asserted. It may be cleared by writing it to a 1; writing it to a 0 has no effect. When the PPERM bit in the EENAB register is set, the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the EATTR register.
Page 122: Ppc Error Address Register
ESTAT register. The register’s contents are not defined when the XDPE, PPER or PSER bits are set in the ESTAT register. Address $FEFF0028 0 1 2 3 4 5 6 7 8 9 Name EAADR Operation Reset $00000000 http://www.motorola.com/computer/literature 2-83...
Page 123: Ppc Error Attribute Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Error Attribute Register The Error Attribute Register (EATTR) captures attribute information on the various errors that the PHB can detect. If the XDPE, PPER or PSER bits are set in the ESTAT register, the contents of the EATTR register are zero.
Page 124 COMMx PCI Command. This field contains the PCI command of the PCI transfer in which the error occurred. BYTEx PCI Byte Enable. This field contains the PCI byte enables of the PCI transfer in which the error occurred. A set bit designates a selected byte. http://www.motorola.com/computer/literature 2-85...
Page 125: Pci Interrupt Acknowledge Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI Interrupt Acknowledge Register The PCI Interrupt Acknowledge Register (PIACK) is a read only register that is used to initiate a single PCI Interrupt Acknowledge cycle. Any single byte or combination of bytes may be read from, and the actual byte enable pattern used during the read will be passed on to the PCI bus.
Page 126: Ppc Slave Address (0,1 And 2) Registers
End Address. This field determines the end address of a particular memory area on the PPC bus which will be used to access PCI bus resources. The value of this field will be compared with the upper 16 bits of the incoming PPC address. http://www.motorola.com/computer/literature 2-87...
Page 127: Ppc Slave Offset/Attribute (0, 1 And 2) Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Slave Offset/Attribute (0, 1 and 2) Registers Address XSOFF0/XSATT0 - $FEFF0044 XSOFF1/XSATT1 - $FEFF004C XSOFF2/XSATT2 - $FEFF0054 Name XSOFFx XSATTx Operation Reset $0000 The PPC Slave Offset Registers (XSOFF0, XSOFF1, and XSOFF2) contains offset information associated with the mapping of PPC memory space to PCI memory I/O space.
Page 128: Ppc Slave Address (3) Register
PCI CONFIG_ADDRESS ($80000CF8) and CONFIG_DATA ($80000CFC) registers. The power up value of XSADD3 (and XSOFF3/XSATT3) are set to allow access to these special register spaces without PPC register initialization. http://www.motorola.com/computer/literature 2-89...
Page 129: Ppc Slave Offset/Attribute (3) Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The fields within XSADD3 are defined as follows: START Start Address. This field determines the start address of a particular memory area on the PPC bus which will be used to access PCI bus resources. The value of this field will be compared with the upper 16 bits of the incoming PPC address.
Page 130: Wdtxcntl Registers
Name RELOAD Operation Reset $7 or $8 The Watchdog Timer Control Registers (WDT1CNTL and WDT2CNTL) are used to provide control information to the watchdog timer functions within the PHB. The fields within WDTxCNTL registers are defined as follows: http://www.motorola.com/computer/literature 2-91...
Page 131 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Key. This field is used during the two step arming process of the Control register. This field is sensitive to the following data patterns: PATTERN_1 = $55 PATTERN_2 = $AA The Control register will be in the armed state if PATTERN_1 is written to the KEY field.
Page 132 32,768 us 32 min RELOAD Reload. This field is written with a value that will be used to reload the timer. The RELOAD field may only be modified on the second step of a successful two step arming process. http://www.motorola.com/computer/literature 2-93...
Page 133: Wdtxstat Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller WDTxSTAT Registers Address WDT1STAT - $FEFF0064 WDT2STAT - $FEFF006C WDTxSTAT Name COUNT Operation Reset The Watchdog Timer Status Registers (WDT1STAT and WDT2STAT) are used to provide status information from the watchdog timer functions within the PHB.
Page 134: Pci Registers
Table 2-17. PCI Configuration Register <--- Bit 0 9 8 7 6 5 4 3 2 1 0 DEVID VENID STATUS COMMAND CLASS REVID HEADER MIBAR MMBAR $18 - $7C PSADD0 PSOFF0 PSATT0 PSADD1 PSOFF1 PSATT1 PSADD2 PSOFF2 PSATT2 PSADD3 PSOFF3 PSATT3 http://www.motorola.com/computer/literature 2-95...
Page 135: Vendor Id/ Device Id Registers
VENID Vendor ID. This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the PPC Registers. DEVID Device ID. This register identifies the particular device.
Page 136: Pci Command/ Status Registers
SERR System Error Enable. This bit enables the SERR_ output pin. If clear, the PHB will never drive SERR_. If set, the PHB will drive SERR_ active when a system error is detected. http://www.motorola.com/computer/literature 2-97...
Page 137 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The Status Register (STATUS) is used to record information for PCI bus related events. The bits within the STATUS register are defined as follows: P66M PCI66 MHz. This bit indicates the PHB is capable of supporting a 66.67 MHz PCI bus.
Page 138: Header Type Register
PCI Bridge Device Subclass Code PCI Host Bridge Program Class Code Not Used Header Type Register Offset Name HEADER Operation Reset The Header Type Register (Header) identifies the PHB as the following: Header Type: $00 - Single Function Configuration Header http://www.motorola.com/computer/literature 2-99...
Page 139: Mpic I/O Base Address Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC I/O Base Address Register Offset 0 9 8 7 6 5 4 3 2 1 0 Name MIBAR BASE Operation Reset $0000 $0000 The MPIC I/O Base Address Register (MIBAR) controls the mapping of the MPIC control registers in PCI I/O space.
Page 140: Pci Slave Address (0,1,2, And 3) Registers
PCI Slave Address (0,1,2, and 3) Registers Offset PSADD0 - $80 PSADD1 - $88 PSADD2 - $90 PSADD3 - $98 0 9 8 7 6 5 4 3 2 1 0 Name PSADDx START Operation Reset $0000 $0000 http://www.motorola.com/computer/literature 2-101...
Page 141: Pci Slave Attribute/ Offset (0,1,2 And 3) Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave Address Registers (PSADDx) contain address information associated with the mapping of PCI memory space to PPC memory space. The fields within the PSADDx registers are defined as follows: START Start Address.
Page 142 Read Any FIFO Threshold. This field is used by the PHB to determine a FIFO threshold at which to continue prefetching data from local memory during PCI read and read line transactions. This threshold applies to subsequent prefetch reads since all initial prefetch reads http://www.motorola.com/computer/literature 2-103...
Page 143: Config_Address Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller will be four cache lines. This field is only applicable if read-ahead has been enabled. The encoding of this field is shown in the table above. WXFT Write FIFO Threshold 4 Cache lines 3 Cache lines 2 Cache lines 1 Cache lines...
Page 144 0 1 2 3 4 5 6 7 8 9 Name CONFIG_ADDRESS Operation Reset Perspective from the PPC bus in Little Endian mode: Offset $CFC $CFD $CFE $CFF Bit (DL) 0 1 2 3 4 5 6 7 8 9 Name CONFIG_ADDRESS Operation Reset http://www.motorola.com/computer/literature 2-105...
Page 145 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The register fields are defined as follows: Register Number. Configuration Cycles: Identifies a target double word within a target’s configuration space. This field is copied to the PCI AD bus during the address phase of a Configuration cycle.
Page 146: Config_Data Register
Perspective from the PPC bus in Little Endian mode: Offset $CF8 $CF9 $CFA $CFB Bit (DH) 0 1 2 3 4 5 6 7 8 9 Name CONFIG_DATA Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’ Operation Reset http://www.motorola.com/computer/literature 2-107...
Page 147: Mpic Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC Registers The following conventions are used in the Hawk register charts: R - Read Only field. R/W - Read/Write field. S - Writing a ONE to this field sets this field. C - Writing a ONE to this field clears this field.
Page 148: Table 2-19. Mpic Register Map
INT. SRC. 2 VECTOR-PRIORITY REGISTER $10040 INT. SRC. 2 DESTINATION REGISTER $10050 INT. SRC. 3 VECTOR-PRIORITY REGISTER $10060 INT. SRC. 3 DESTINATION REGISTER $10070 INT. SRC. 4 VECTOR-PRIORITY REGISTER $10080 INT. SRC. 4 DESTINATION REGISTER $10090 INT. SRC. 5 VECTOR-PRIORITY REGISTER $100a0 http://www.motorola.com/computer/literature 2-109...
Page 149 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-19. MPIC Register Map (Continued) 0 9 8 7 6 5 4 3 2 1 0 INT. SRC. 5 DESTINATION REGISTER $100b0 INT. SRC. 6 VECTOR-PRIORITY REGISTER $100c0 INT. SRC. 6 DESTINATION REGISTER $100d0 INT.
Page 150 $21070 CURRENT TASK PRIORITY REGISTER PROC. 1 $21080 IACK REGISTER $210a0 EOI REGISTER $210b0 Feature Reporting Register Offset $01000 0 9 8 7 6 5 4 3 2 1 0 Name FEATURE REPORTING NIRQ NCPU Operation Reset $00F http://www.motorola.com/computer/literature 2-111...
Page 151 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller NIRQ NUMBER OF IRQs. The number of the highest external IRQ source supported. The IPI, Timer, and PHB Detected Error interrupts are excluded from this count. NCPU NUMBER OF CPUs. The number of the highest physical CPU supported.
Page 152: Table 2-20. Cascade Mode Encoding
When this register bit is set to 0, a tie in external interrupt processing will always go to processor 0 (Mode used on Version $02 of MPIC). Table 2-21. Tie Mode Encoding Mode Processor 0 always selected Swap between Processor’s http://www.motorola.com/computer/literature 2-113...
Page 153: Vendor Identification Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Vendor Identification Register Offset $01080 0 9 8 7 6 5 4 3 2 1 0 Name VENDOR IDENTIFICATION Operation Reset There are two fields in the Vendor Identification Register which are not defined for the MPIC implementation but are defined in the MPIC specification.
Page 154: Ipi Vector/Priority Registers
PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-115...
Page 155: Spurious Vector Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Spurious Vector Register Offset $010E0 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation Reset VECTOR This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch. Timer Frequency Register Offset $010F0...
Page 156: Timer Current Count Registers
Count Inhibit bit is the Base Count Register is zero. When the timer counts down to zero, the Current Count register is reloaded from the Base Count register and the timer’s interrupt becomes pending in MPIC processing. http://www.motorola.com/computer/literature 2-117...
Page 157: Timer Basecount Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timer Basecount Registers Offset Timer 0 - $01110 Timer 1 - $01150 Timer 2 - $01190 Timer 3 - $011D0 0 9 8 7 6 5 4 3 2 1 0 Name TIMER BASECOUNT Operation Reset...
Page 158: Timer Vector/Priority Registers
PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-119...
Page 159: Timer Destination Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timer Destination Registers Offset Timer 0 - $01130 Timer 1 - $01170 Timer 2 - $011B0 Timer 3 - $011F0 0 9 8 7 6 5 4 3 2 1 0 Name TIMER DESTINATION Operation Reset...
Page 160 PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-121...
Page 161: External Source Destination Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller External Source Destination Registers Offset Int Src 0 - $10010 Int Src 1-> Int Src 15 - $10030 -> $101F0 0 9 8 7 6 5 4 3 2 1 0 Name EXTERNAL SOURCE DESTINATION Operation Reset...
Page 162: Hawk Internal Error Interrupt Vector/Priority Register
PRIORITY. Interrupt priority 0 is the lowest and 15 is the highest. Note that a priority level of 0 will not enable interrupts. VECTOR VECTOR. This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-123...
Page 163: Hawk Internal Error Interrupt Destination Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Hawk Internal Error Interrupt Destination Register Offset $10210 0 9 8 7 6 5 4 3 2 1 0 Name HAWK INTERNAL ERROR INTERRUPT DESTINATION Operation Reset This register indicates the possible destinations for the Hawk internal error interrupt source.
Page 164: Current Task Priority Registers
$FF hex. The associated bit in the Interrupt Pending Register is cleared. Reading this register will update the In-Service register. VECTOR Vector. This vector is returned when the Interrupt Acknowledge register is read. http://www.motorola.com/computer/literature 2-125...
Page 165: End-Of-Interrupt Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller End-of-Interrupt Registers Offset Processor 0 $200B0 Processor 1 $210B0 0 9 8 7 6 5 4 3 2 1 0 Name Operation Reset END OF INTERRUPT. There is one EOI register per processor.
Page 166: Introduction
3System Memory Controller (SMC) Introduction The SMC in the Hawk ASIC is equivalent to the former Falcon Pair portion of a Falcon/Raven chipset. The SMC has interfaces between the PPC60x bus and SDRAM, ROM/Flash, and its Control and Status Register sets (CSR).
Page 167: Block Diagrams
System Memory Controller (SMC) ROM/Flash Interface – Two blocks with each block being 16 or 64 bits wide. – Programmable access time on a per-block basis. C master interface. External status/control register support Block Diagrams Figure 3-1 depicts a Hawk as it would be connected with SDRAMs in a system.
Page 168: Figure 3-2. Hawk's System Memory Controller Internal Data Paths
Block Diagrams PowerPC SDRAM Side Side (8 Bits) Latched D (64 Bits) (64 Bits) (8 Bits) (8 Bits) (8 Bits) Uncorrected Data (64 Bits) Figure 3-2. Hawk’s System Memory Controller Internal Data Paths http://www.motorola.com/computer/literature...
Page 169: Figure 3-3. Overall Sdram Connections
System Memory Controller (SMC) D0/D1_CS_ C0/C1_CS_ B0/B1_CS_ A0/A1_CS_ BA,RA,RAS_, CAS_,WE_,DQM RD0-63 CKD0-7 SDRAM SDRAM SDRAM SDRAM BLOCK A BLOCK B BLOCK C BLOCK D Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers) Computer Group Literature Center Web Site...
Page 170: Figure 3-4. Hawk's System Memory Controller Block Diagram
INTERFACE CONTROL REFRESHER MEM Addr PPC60x Attr PPC60x SDRAM /SCRUBBER ADDRESS ADDRESS ARBITER DECODER MULTIPLEXOR PPC60x Addr STATUS SDRAM /CONTROL ERROR REGISTERS JTAG LOGGER INTERFACE MEM Data PPC60x Data DATA MULTIPLEXOR Figure 3-4. Hawk’s System Memory Controller Block Diagram http://www.motorola.com/computer/literature...
Page 171: Functional Description
System Memory Controller (SMC) Functional Description The following sections describe the logical function of the SMC. The SMC has interfaces between the PowerPC bus and SDRAM, ROM/Flash, and its control and status register sets (CSR). SDRAM Accesses Four-beat Reads/Writes The SMC performs best when doing bursting (4-beat accesses). This is made possible by the burst nature of synchronous DRAMs.
Page 172: Page Holding
1-1-1 half of the time and 3- SDRAM Bank Active - Page Hit 1-1-1 the other half. 4-Beat Write after idle, 4-1-1-1 SDRAM Bank Active or Inactive 4-Beat Write after 4-Beat Write, 6-1-1-1 SDRAM Bank Active - Page Miss http://www.motorola.com/computer/literature...
Page 173 System Memory Controller (SMC) Table 3-1. 60 x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAMs (CAS_latency of 2) (Continued) Access Type Access Time Comments 4-Beat Write after 4-Beat Write, 3-1-1-1 3-1-1-1 for the second burst write after idle.
Page 174: Sdram Organization
If the data transfer will be a write, the SMC begins latching data from the PowerPC data bus as soon as any previously latched data is no longer needed and the PPC60x data bus is available. http://www.motorola.com/computer/literature...
Page 175: Ppc60X Data Parity
System Memory Controller (SMC) PPC60x Data Parity The Hawk has 8 DP pins for generating and checking PPC60x data bus parity. During read cycles that access the SMC, the Hawk generates the correct value on DP0-DP7 so that each data byte lane along with its corresponding DP signal has odd parity.
Page 176: Cache Coherency
When the PPC60x bus master requests a single-beat write to SDRAM, the SMC performs a full width read cycle to SDRAM, merges in the appropriate PPC60x bus write data, and writes full width back to SDRAM. http://www.motorola.com/computer/literature 3-11...
Page 177: Error Reporting
System Memory Controller (SMC) Error Reporting The SMC checks data from the SDRAM during single- and four-beat reads, during single-beat writes, and during scrubs. Table 3-2 shows the actions it takes for different errors during these accesses 60x. Note that the SMC does not assert TEA_ on double-bit errors. In fact, the SMC does not have a TEA_ signal pin and it assumes that the system does not implement TEA_.
Page 178: Error Logging
The logging of errors that occur during scrub can be enabled/disabled in software. Refer to the Error Logger Register section in this chapter for more information. http://www.motorola.com/computer/literature 3-13...
Page 179: Rom/Flash Interface
System Memory Controller (SMC) ROM/Flash Interface The SMC provides the interface for two blocks of ROM/Flash. Each block provides addressing and control for up to 64Mbytes. Note that no ECC error checking is provided for the ROM/Flash. The ROM/Flash interface allows each block to be individually configured by jumpers and/or by software as follows: 1.
Page 180 In order to place code correctly in the ROM/Flash devices, address mapping information is required. Table 3-3 shows how PPC60x addresses map to the ROM/Flash addresses when ROM/Flash is 16 bits wide. Table shows how they map when Flash is 64 bits wide. http://www.motorola.com/computer/literature 3-15...
Page 181: Table 3-3. Ppc60X To Rom/Flash (16 Bit Width)
System Memory Controller (SMC) Table 3-3. PPC60x to ROM/Flash (16 Bit Width) Address Mapping PPC60x A0-A31 ROM/Flash A22-A0 ROM/Flash Device Selected $XX000000 $000000 Upper $XX000001 $000001 Upper $XX000002 $000002 Upper $XX000003 $000003 Upper $XX000004 $000000 Lower $XX000005 $000001 Lower $XX000006 $000002 Lower $XX000007...
Page 182: Table 3-4. Ppc60X To Rom/Flash (64 Bit Width) Address Mapping (Continued)
$000001 Lower $X000000E $000001 Lower $X000000F $000001 Lower $X3FFFFF0 $7FFFFE Upper $X3FFFFF1 $7FFFFE Upper $X3FFFFF2 $7FFFFE Upper $X3FFFFF3 $7FFFFE Upper $X3FFFFF4 $7FFFFE Lower $X3FFFFF5 $7FFFFE Lower $X3FFFFF6 $7FFFFE Lower $X3FFFFF7 $7FFFFE Lower $X3FFFFF8 $7FFFFF Upper $X3FFFFF9 $7FFFFF Upper http://www.motorola.com/computer/literature 3-17...
Page 183 System Memory Controller (SMC) Table 3-4. PPC60x to ROM/Flash (64 Bit Width) Address Mapping (Continued) PPC60x A0-A31 ROM/Flash A22-A0 ROM/Flash Device Selected $X3FFFFFA $7FFFFF Upper $X3FFFFFB $7FFFFF Upper $X3FFFFFC $7FFFFF Lower $X3FFFFFD $7FFFFF Lower $X3FFFFFE $7FFFFF Lower $X3FFFFFF $7FFFFF Lower 3-18 Computer Group Literature Center Web Site...
Page 184: Rom/Flash Speeds
4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes) 1-Beat Write Note The information in Table 3-5 applies to access timing when configured for devices with an access time equal to 12 clock periods. http://www.motorola.com/computer/literature 3-19...
Page 185: Table 3-6. Ppc60X Bus To Rom/Flash Access Timing (80Ns @ 100 Mhz)
System Memory Controller (SMC) Table 3-6. PPC60x Bus to ROM/Flash Access Timing (80ns @ 100 MHz) CLOCK PERIODS REQUIRED FOR: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat ACCESS TYPE Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4-Beat Read...
Page 186: Table 3-8. Ppc60X Bus To Rom/Flash Access Timing (30Ns @ 100 Mhz)
4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes) 1-Beat Write Note The information in Table 3-8 applies to access timing when configured for devices with an access time equal to 3 clock periods. http://www.motorola.com/computer/literature 3-21...
Page 187: I2C Interface
System Memory Controller (SMC) C Interface The ASIC has an I C (Inter-Integrated Circuit) two-wire serial interface bus: serial clock line (SCL) and serial data line (SDA). This interface has master-only capability and may be used to communicate the configuration information to a slave I C device such as serial EEPROM.
Page 188: I2C Byte Write
The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master’s possession of the I C bus. Figure 3-5 shows the suggested software flow diagram for programming the I C byte write operation. http://www.motorola.com/computer/literature 3-23...
Page 189: Figure 3-5. Programming Sequence For I 2 C Byte Write
System Memory Controller (SMC) DEVICE ADDR WORD ADDR DATA START STOP ACK from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG CMPLT=ACKIN=1? LOAD “WORD ADDR”...
Page 190: I2C Random Read
_cmplt bit for the operation-complete status. The stop sequence will relinquish the ASIC master’s possession of the I C bus. Figure 3-6 shows the suggested software flow diagram for programming the I C random read operation. http://www.motorola.com/computer/literature 3-25...
Page 191 System Memory Controller (SMC) DEVICE ADDR WORD ADDR x DEVICE ADDR START START DATA x STOP ACK and DATA from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG...
Page 192: I2C Current Address Read
The stop sequence will relinquish the ASIC master’s possession of the I C bus. Figure 3-7 shows the suggested software flow diagram for programming the I C current address read operation. http://www.motorola.com/computer/literature 3-27...
Page 193 System Memory Controller (SMC) DATA of (last ADDR+1) DEVICE ADDR START STOP ACK and DATA from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+RD BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG CMPLT=ACKIN=1?
Page 194: I2C
The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master’s possession of the I C bus. Figure 3-8 shows the suggested software flow diagram for programming the I C page write operation. http://www.motorola.com/computer/literature 3-29...
Page 195 System Memory Controller (SMC) DEVICE ADDR WORD ADDR 1 DATA 1 DATA n START STOP ACK from Slave Device BEGIN READ I C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO C TRANSMITTER DATA REG READ I C STATUS REG CMPLT=ACKIN=1?
Page 196: I2C Sequential Read
C Status Register) and the i2_cmplt bit has also been tested for proper status, the I C master controller responds with an acknowledge and the system software may then read the data by polling the I C Receiver Data Register. http://www.motorola.com/computer/literature 3-31...
Page 197 System Memory Controller (SMC) As long as the slave device receives an acknowledge, it will continue to increment the word address and serially clock out sequential data words. The I C sequential read operation is terminated when the I C master controller does not respond with an acknowledge.
Page 198 READ I C STATUS REG READ I C STATUS REG CMPLT=ACKIN=1? CMPLT=1? Stop condition should be generated to abort the transfer after a software wait loop (~1ms) has been expired Figure 3-9. Programming Sequence for I C Sequential Read http://www.motorola.com/computer/literature 3-33...
Page 199: Refresh/Scrub
System Memory Controller (SMC) Refresh/Scrub The SMC performs refresh by doing a burst of 4 CAS-Before-RAS (CBR) refresh cycles to each block of SDRAM once every 60 microseconds. It performs scrubs by replacing every 128th refresh burst with a read cycle to 8 bytes in each block of SDRAM.
Page 200: Chip Configuration
PPC60x data bus. CSR read accesses can have a size of 1, 2, 4, or 8 bytes with any alignment. CSR write accesses are restricted to a size of 1 or 4 bytes and they must be aligned. http://www.motorola.com/computer/literature 3-35...
Page 201: Register Summary
System Memory Controller (SMC) Register Summary Table 3-9 shows a summary of the internal and external register set. Table 3-9. Register Summary BIT # ----> FEF80000 VENDID DEVID REVID PU STAT FEF80008 RAM A RAM B RAM C RAM D FEF80010 FEF80018 RAM A BASE...
Page 202 RAM E RAM F RAM G RAM H FEF800C0 FEF800C8 RAM E BASE RAM F BASE RAM G BASE RAM H BASE FEF800D0 APE_TT APE_AP FEF800E0 FEF800E8 APE_A FEF80100 CTR32 FEF88300 FEF88000 EXTERNAL REGISTER SET FEF8FFF8 BIT # ----> http://www.motorola.com/computer/literature 3-37...
Page 203: Detailed Register Bit Descriptions
System Memory Controller (SMC) Notes 1. All empty bit fields are reserved and read as zeros. 2. All status bits are shown in italics. 3. All control bits are shown with underline. 4. All control-and-status bits are shown with italics and underline.
Page 204: Vendor/Device Register
Reset $1057 $4803 VENDID This read-only register contains the value $1057. It is the vendor number assigned to Motorola Inc. DEVID This read-only register contains the value $4803. It is the device number for the Hawk. Revision ID/General Control Register...
Page 205 System Memory Controller (SMC) Software should only set the tben_en bit when there is no external L2 cache connected to the I2clm_ pin and when there is no external register set. REVID The REVID bits are hard-wired to indicate the revision level of the SMC.
Page 206: Sdram Enable And Size Register (Blocks A, B, C, D)
SDRAM. Table 3-10 shows the block configuration assumed by the SMC for each value of ram siz0-ram siz3. Note that ram e/f/g/h size0-3 are located at $FEF800C0. They operate identically for blocks E-H as these bits do for blocks A-D. http://www.motorola.com/computer/literature 3-41...
Page 207: Table 3-10. Block_A/B/C/D/E/F/G/H Configurations
System Memory Controller (SMC) Table 3-10. Block_A/B/C/D/E/F/G/H Configurations ram a-h Component Number of Block SDRAM siz0-3 Configuration SDRAM SIZE Technology Components In the Block %0000 0MBytes %0001 4Mx16 32MBytes 64Mbit %0010 8Mx8 64MBytes 64Mbit %0011 8Mx16 64MBytes 128Mbit %0100 16Mx4 128MBytes 64Mbit %0101...
Page 208: Sdram Base Address Register (Blocks A/B/C/D)
E-H as these bits do for blocks A-D. Also note that the combination of RAM_X_BASE and ram_x_siz should never be programmed such that SDRAM responds at the same address as the CSR, ROM/Flash, External Register Set, or any other slave on the PowerPC bus. http://www.motorola.com/computer/literature 3-43...
Page 209: Clk Frequency Register
System Memory Controller (SMC) CLK Frequency Register Address $FEF80020 Name CLK FREQUENCY Operation READ/WRITE READ ZERO READ ZERO Reset 64 P CLK FREQUENCY These bits should be programmed with the hexadecimal value of the operating CLOCK frequency in MHz (i.e. $42 for 66 MHz).
Page 210: Ecc Control Register
PPC60x bus to access check-bit data rather than normal data. The data path used for reading and writing check bits is D0-D7. Each 8-bit check-bit location services 64 bits of normal data. Figure 3-10 shows the relationship between normal data and check-bit data. http://www.motorola.com/computer/literature 3-45...
Page 211: Figure 3-10. Read/Write Check-Bit Data Paths
System Memory Controller (SMC) Normal View of Data (rwcb=0) 64 bits Check-bit View (rwcb=1) Figure 3-10. Read/Write Check-bit Data Paths Note that if test software attempts to force a single-bit error to a location using the rwcb function, the scrubber may correct the location before the test software gets a chance to check for the single-bit error.
Page 212 When dpien is set, the logging of a PPC60x data parity error causes the int bit to be set if it is not already. When the int bit is set, the Hawk’s internal error interrupt is asserted. http://www.motorola.com/computer/literature 3-47...
Page 213 System Memory Controller (SMC) sien When sien is set, the logging of a single-bit error causes the int bit to be set if it is not already. When the int bit is set, the Hawk’s internal error interrupt is asserted. mien When mien is set, the logging of a non-correctable error causes the int bit to be set if it is not already.
Page 214: Error Logger Register
It is cleared by the logging of a single-bit error. It is undefined after power-up reset. The syndrome code is meaningless if its embt bit is set. http://www.motorola.com/computer/literature 3-49...
Page 215 System Memory Controller (SMC) esbt esbt is set by the logging of a single-bit error. It is cleared by the logging of a multiple-bit error. When the SMC logs a single-bit error, the syndrome code indicates which bit was in error. Refer to the section on SDRAM ECC Codes. ERR_SYNDROME ERR_SYNDROME reflects the syndrome value at the last logging of an error.
Page 216: Error_Address Register
Each time the SMC performs a refresh burst, the scrub prescale counter increments by one. When the scrub prescale counter reaches the value stored in this register, it clears and resumes counting starting at 0. http://www.motorola.com/computer/literature 3-51...
Page 217: Scrub Address Register
System Memory Controller (SMC) Note that when this register is all 0’s, the scrub prescale counter does not increment, disabling any scrubs from occurring. Since SCRUB_FREQUENCY is cleared to 0’s at power-up reset, scrubbing is disabled until software programs a non-zero value into it. Scrub Address Register Address $FEF80048...
Page 218: Rom A Base/Size Register
ROM/Flash being used for Block A. When rom_a_64 is cleared, Block A is 16 bits wide, where each half of SMC interfaces to 8 bits. When rom_a_64 is set, Block A is 64 bits wide, where http://www.motorola.com/computer/literature 3-53...
Page 219: Table 3-11. Rom Block A Size Encoding
System Memory Controller (SMC) each half of the SMC interfaces to 32 bits. rom_a_64 matches the value that was on the RD2 pin at power-up reset. It cannot be changed by software. rom a siz The rom a siz control bits are the size of ROM/Flash for Block A.
Page 220: Table 3-13. Read/Write To Rom/Flash
No Response write 4-byte Misaligned No Response write 4-byte Aligned No Response write 4-byte Aligned Normal termination, but no write to ROM/Flash write 4-byte Aligned Normal termination, write occurs to ROM/Flash write 2,3,5,6,7, No Response 8,32-byte read Normal Termination http://www.motorola.com/computer/literature 3-55...
Page 221: Rom B Base/Size Register
System Memory Controller (SMC) ROM B Base/Size Register Address $FEF80058 Name ROM B BASE Operation READ/WRITE READ ZERO Reset $FF4 PL Writes to this register must be enveloped by a period of time in which no accesses to ROM/Flash Block B, occur. A simple way to provide the envelope is to perform at least two accesses to this (or another of the SMC’s registers before and after the write).
Page 222: Table 3-14. Rom Block B Size Encoding
RD1 pin. rom b en When rom b en is set, accesses to Block B ROM/Flash in the address range selected by ROM B BASE are enabled. When rom b en is cleared they are disabled. http://www.motorola.com/computer/literature 3-57...
Page 223: Rom Speed Attributes Registers
System Memory Controller (SMC) rom b we When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is cleared they are disabled. Refer back to Table 3-13 for more details. ROM Speed Attributes Registers Address $FEF80060 Name...
Page 224: Table 3-15. Rom Speed Bit Encodings
ROM/Flash, Bank B, occur. A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC’s registers before and after the write. http://www.motorola.com/computer/literature 3-59...
Page 225: Data Parity Error Log Register
System Memory Controller (SMC) Data Parity Error Log Register Address $FEF80068 Name GWDP DPE_DP Operation READ ONLY READ/WRITE Reset 0 PL dpelog dpelog is set when a parity error occurs on the PPC60x data bus during a PPC60x data cycle whose parity the SMC is qualified to check.
Page 226: Data Parity Error Address Register
DPE_DH is the value on the upper half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk. It is updated only when dpelog goes from 0 to 1. http://www.motorola.com/computer/literature 3-61...
Page 227: Data Parity Error Lower Data Register
System Memory Controller (SMC) Data Parity Error Lower Data Register Address $FEF80080 Name DPE_DL Operation READ ONLY Reset 0 PL DPE_DL DPE_DL is the value on the lower half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk.
Page 228: I2C Clock Prescaler Register
After the start sequence and the I C Transmitter Data Register contents have been transmitted, the I C master controller will automatically clear the i2_start bit and then set the i2_cmplt bit in the I C Status Register. http://www.motorola.com/computer/literature 3-63...
Page 229 System Memory Controller (SMC) i2_stop When set, the I C master controller generates a stop sequence on the I C bus on the next dummy write (data=don’t care) to the I C Transmitter Data Register and clears the i2_cmplt bit in the I C Status Register.
Page 230: I2C Transmitter Data Register
I Receiver Data Register. If a value is written to I2_DATAWR (data=don’t care) when the i2_stop and i2_enbl bits in the I Control Register are set, a stop sequence is generated. http://www.motorola.com/computer/literature 3-65...
Page 231: I2C Receiver Data Register
System Memory Controller (SMC) C Receiver Data Register Address $FEF800B0 Name I2_DATARD Operation READ ZERO READ ZERO READ ZERO READ Reset 0 PL I2_DATARD The I2_DATARD contains the receive byte for I C data transfers. During I C sequential read operation, the current receive byte must be read before any new one can be brough in.
Page 232: Sdram Base Address Register (Blocks E/F/G/H)
PowerPC60x address bits 0 - 7. For larger SDRAM sizes, the lower significant bits of RAM E/F/G/HBASE are ignored. This means that the block’s base address will always appear at an even multiple of its size. Remember that bit 0 is MSB. http://www.motorola.com/computer/literature 3-67...
Page 233: Sdram Speed Attributes Register
System Memory Controller (SMC) Note that RAM A/B/C/D BASE are located at $FEF80018 (refer to the section titled SDRAM Base Address Register (Blocks A/B/C/D) for more information). They operate the same for blocks A-D as these bits do for blocks E-H. Also note that the combination of RAM_X_BASE and ram_x_siz should never be programmed such that SDRAM responds at the same address as the CSR, ROM/Flash,...
Page 234: Table 3-16. Trc Encoding
%111 tras0,1 Together tras0,1 determine the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its tRAS parameter. These bits are encoded as follows: Table 3-17. tras Encoding tras0,1 Minimum Clocks for tras http://www.motorola.com/computer/literature 3-69...
Page 235: Address Parity Error Log Register
System Memory Controller (SMC) swr_dpl swr_dpl causes the SMC to always wait until four clocks after the write command portion of a single write before allowing a precharge to occur. This function may not be required. If such is the case, swr_dpl can be cleared by software. tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Tdp parameter.
Page 236: Address Parity Error Address Register
Name APE_A Operation READ ONLY Reset 0 PL APE_A APE_A is the address of the last PPC60x address bus parity error that was logged by the Hawk. It is updated only when apelog goes from 0 to 1. http://www.motorola.com/computer/literature 3-71...
Page 237: 32-Bit Counter
System Memory Controller (SMC) 32-Bit Counter Address $FEF80100 Name CTR32 Operation READ/WRITE Reset 0 PL CTR32 CTR32 is a 32-bit, free-running counter that increments once per microsecond if the CLK_FREQUENCY register has been programmed properly. Notice that CTR32 is cleared by power-up and local reset. Note When the system clock is a fractional frequency, such as 66.67MHz, CTR32 will count at a fractional amount faster or...
Page 238: Tben Register
READ ZERO Reset The tben Register is only enabled when the tben_en bit in the Revision ID/General Control Register is set. When tben_en is cleared, the External Register Set interface is enabled and appears in its designated range. http://www.motorola.com/computer/literature 3-73...
Page 239: Software Considerations
System Memory Controller (SMC) When tben_en is set, the External Register Set interface is disabled and the SMC does not respond to accesses in its designated range except that it responds to the address of this, tben register. p1_tben When the tben_en bit is set, the L2CLM_ input pin becomes the P1_TBEN output pin and it tracks the value on p1_tben.
Page 240: Writing To The Control Registers
SDRAM Speed Attributes The SDRAM speed attributes come up from power-up reset initialized to the slowest settings that Hawk is capable of. This allows SDRAM accesses to be performed before the SDRAM speed attributes are known. http://www.motorola.com/computer/literature 3-75...
Page 241: Sdram Size
System Memory Controller (SMC) An example of a need for this is when software requires some working memory that it can use while gathering and evaluating SDRAM device data from serial EEPROM’s. Once software knows the SDRAM speed parameters for all blocks, it should discontinue accessing SDRAM for at least one refresh period before and after it programs the SDRAM speed attribute bits.
Page 242: Sdram Control Registers Initialization Example
Check SPD byte 18 to determine which CAS latencies are supported. b. If a CAS latency of 2 is supported, then go to step 3. Otherwise, a CAS latency of 3 is all that is supported for this block. http://www.motorola.com/computer/literature 3-77...
Page 243: Table 3-18. Deriving Tras, Trp, Trcd And Trc Control Bit Values From Spd Information
System Memory Controller (SMC) c. If a CAS latency of 2 is supported, check SPD byte 23 to determine the CAS_latency _2 cycle time. If the CAS_latency_2 cycle time is less than or equal to the period of the system clock then this block can operate with a CAS latency of 2.
Page 244 9.0 < tRC_CLK <= 10.0 trc =%010 tRP)/T bits 5,6,7 (SPD Bytes 10.0 < tRC_CLK <= trc =%011 30 and 27) (T = CLK Period (trc) 11.0 in nanoseconds) 11.0 < tRC_CLK illegal See Notes 7, 8 and 9 http://www.motorola.com/computer/literature 3-79...
Page 245 System Memory Controller (SMC) Notes 1. Use tRAS from the SDRAM block that has the slowest tRAS. 2. tRAS_CLK is tRAS expressed in CLK periods. 3. Use tRP from the SDRAM block that has the slowest tRP. 4. tRP_CLK is tRP expressed in CLK periods. 5.
Page 246: Table 3-19. Programming Sdram Siz Bits
32-bit counter to increment at least 100 times. (Refer to the section titled “32-Bit Counter” for more information). Note that the refdis control bit must not be set in the ECC Control Register. http://www.motorola.com/computer/literature 3-81...
Page 247 System Memory Controller (SMC) 8. Now that at least one refresh has occurred since SDRAM was last accessed, it is okay to write to the SDRAM control registers. a. Program the SDRAM Speed Attributes Register using the information obtained in steps 3 and 4 and the fact that the swr_dp and tdp bits should be set to 1’s.
Page 248: Optional Method For Sizing Sdram
$00000000 - $20000000. (Refer to the section on ROM A Base/Size Register and ROM B Base/Size Register for more information.) g. Make sure that no other devices are set up to respond in the range $00000000 - $20000000. http://www.motorola.com/computer/literature 3-83...
Page 249 System Memory Controller (SMC) 2. For each of the Blocks A through H: a. Set the block’s base address to $00000000. Refer to the sections titled SDRAM Base Address Register (Blocks A/B/C/D) and SDRAM Enable and Size Register (Blocks E,F,G,H). b.
Page 250: Table 3-20. Address Lists For Different Block Size Checks
2. 8Mx16 and 8Mx8 are the same. The same idea that applies to 16Mx8 and 16Mx4 applies to them. 3. This needed only to check for non-zero size. 3. Wait enough time to allow at least 1 SDRAM refresh to occur before beginning any SDRAM accesses. http://www.motorola.com/computer/literature 3-85...
Page 251: Ecc Codes
System Memory Controller (SMC) ECC Codes When the Hawk reports a single-bit error, software can use the syndrome that was logged by the Hawk to determine which bit was in error. Table 3-21 shows the syndrome for each possible single bit error. Table 3-22 shows the same information ordered by syndrome.
Page 252: Table 3-22. Single Bit Errors Ordered By Syndrome Code
$AC rd14 rd13 rd44 ckd4 rd53 rd50 rd46 rd49 rd43 rd39 rd63 rd40 rd16 rd17 rd60 rd62 rd59 rd56 rd12 rd11 rd10 rd61 rd58 rd57 rd20 rd28 rd36 http://www.motorola.com/computer/literature 3-87...
Page 253: Introduction
4Hawk Programming Details Introduction This chapter contains details of several programming functions associated with the Hawk ASIC chip. PCI Arbitration PCI arbitration must be provided by the host board. Hawk MPIC External Interrupts The MCPN765 Hawk MPIC is fully compliant with the industry standard Multi-Processor Interrupt Controller Specification.
Page 254: 8259 Interrupts
Hawk Programming Details Table 4-1. MPIC Interrupt Assignments (Continued) MPIC Edge/Level Polarity Interrupt Source Notes IRQ9 Level PMC INTA# or PMC2 INTB# IRQ10 Level PMC INTB# or PMC2 INTC# IRQ11 Level PMC INTC# or PMC2 INTD# IRQ12 Level PMC INTD# or PMC2 INTA# IRQ13 Level PCI-Ethernet 2 (connected to J3)
Page 255: Table 4-2. Pbc Isa Interrupt Assignments
21554 Secondary Interrupt IRQ6 IRQ6 Edge High Not Used IRQ7 IRQ7 Edge High Not Used Notes 1. Internally generated by the PBC. 2. These interrupt sources must be routed to the appropriate ISA IRQ using the PBC interrupt routing registers. http://www.motorola.com/computer/literature...
Page 256: Exceptions
Hawk Programming Details Exceptions Sources of Reset There are five potential reset sources on the MCPN765 series. They are as follows: 1. Power-On Reset 2. PMC PCI RST# 3. Watchdog Timer Reset via the Hawk Watchdog 2 Timer output 4. Software generated Module Reset 5.
Page 257: Error Notification And Handling
Generate Machine Check Interrupt to the Processor(s) if so enabled PERR# Detected Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor(s) if so enabled SERR# Detected Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor(s) if so enabled http://www.motorola.com/computer/literature...
Page 258: Endian Issues
Hawk Programming Details Endian Issues The MCPN765 series supports both Little and Big-Endian software. Because the PowerPC processor is inherently big endian, and PCI is inherently Little-Endian, it is easy to misinterpret the processing scheme. For that reason, provisions have been made to accommodate the handling of endian issues within the MCPN765.
Page 259: Figure 4-2. Little-Endian Mode
Endian Issues Little-Endian PROGRAM Little Endian Big Endian EA Modification (XOR) Hawk DRAM 60X System Bus Hawk Big-Endian EA Modification Little-Endian PCI Local Bus Figure 4-2. Little-Endian Mode http://www.motorola.com/computer/literature...
Page 260: Processor/Memory Domain
Hawk Programming Details Processor/Memory Domain The MPC750 processor can operate in both Big-Endian and Little-Endian modes. However, it always treats the external processor/memory bus as Big-Endian by performing address rearrangement and reordering when running in Little-Endian mode. The MPIC registers inside the Hawk, the registers inside the SMC, the SDRAM, the ROM/FLASH, and the system registers always appear as Big-Endian.
Page 261: Motorola Computer Group Documents
ARelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature...
Page 262: Manufacturers' Documents
Table A-2. Manufacturers’ Documents Publication Document Title Number MPC750 RISC Microprocessor Users Manual MPC750UM/AD Motorola Literature Distribution Center Telephone: (800) 441-2447 or (303) 675-2140 MPC7400 RISC Microprocessor Users Manual MPC7400UM/D Motorola Literature Distribution Center Telephone: (800) 441-2447 or (303) 675-2140...
Page 263: Related Specifications
FAX: (503) 234-6762 Common Mezzanine Card Specification P1386 IEEE Standards Department Draft 2.0 445 Hoes Lane, P.O Box 1331 Piscataway, NJ 08855-1331 PCI Mezzanine Card Specification P1386.1 IEEE Standards Department Draft 2.0 445 Hoes Lane, P.O Box 1331 Piscataway, NJ 08855-1331 http://www.motorola.com/computer/literature...
Page 264 Index Numerics 32-Bit Counter 3-72 big to little-endian data swap 2-39 big-endian mode bit descriptions 3-38 AACK, as used with PPC Slave bit ordering convention access timing (ROM) 3-19, 3-20 block diagram address Hawk Address Parity Error Address Hawk used with SDRAM Register 3-71 Hawk with SDRAMs...
Page 265 Index configuration options on Hawk 3-35 registers 2-19 codes 3-86 Control Register 3-45 requirements on Hawk 3-35 EEPROM type, as used by PHB 2-31 EEPROM access 3-76 contention endian conversion 2-38 between PCI and PPC 2-44 End-of-Interrupt Registers 2-126 handling explained (PHB) 2-45 Error Address Register 3-51...
Page 266 3-74 programming details for Hawk System Memory Controller IPI Vector/Priority Registers 2-115 block diagram Hawk ASIC Hawk latency, PCI Slave 2-25 External Register Bus Summar 1-11 little-endian mode C interface and configuration Lock Resolution, programmable 2-46 information http://www.motorola.com/computer/literature IN-3...
Page 267 Index Interface features Master Command Codes 2-27 Main Memory Master explained mapping, PPC address purpose of interface 2-19 master initiated termination 2-28 registers 2-95 Memory slave 2-22 Base Register 2-100 Slave disconnect scenarios 2-24 Controller slave response command types 2-23 maps Slave with PCI Master 2-26...
Page 268 2-124 PLL Configuration Type Identification rror Address 2-83 Version Register (PVR) Error Attribute 2-84 memory domain Error Enable 2-78 programming details 1-1, Error Status 2-81 programming ROM/Flash devices 3-74 Slave Address 2-89 PVR value Slave Offset/Attribute 2-88, 2-90 http://www.motorola.com/computer/literature IN-5...
Page 269 Index RESET and ABORT Switch data transfers Revision ID Register 2-69 ECC Control Register 3-45 programmable DMA Controller Error Address Register 3-51 Error Logger Register 3-49 Block A Size Encodings 3-54 error logging 3-13 Block B Size Encoding 3-57 External Register Set 3-34 Flash 3-14...
Page 270 Universe chip problems User Configuration Data Vendor ID/ Device ID Registers 2-96 Vendor Identification Register 2-114 Vital Product Data 1-5, VMEbus VPD SROM Watchdog Timer Register 2-43 WDTxCNTL register 2-43 write posting, PHB tuning 2-11 writing to control registers 3-75 http://www.motorola.com/computer/literature IN-7...

Motorola MVME5100 Programmer's Reference Manual

CHAPTER 1 Product Data and Memory Maps

CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

CHAPTER 3 System Memory Controller (SMC)

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