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Lattice Semiconductor MachXO2 Series Usage Manual

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Download this manual See also: User Manual
January 2017
Introduction
Memory errors can occur when high-energy charged particles alter the stored charge in a memory cell in an elec-
tronic circuit. The phenomenon first became an issue in DRAM, requiring error detection and correction for large
memory systems in high-reliability applications. As device geometries have continued to shrink, the probability of
memory errors in SRAM has become significant for some systems. Designers are using a variety of approaches to
minimize the effects of memory errors on system behavior.
SRAM-based PLDs store logic configuration data in SRAM cells. As the number and density of SRAM cells in an
PLD increase, the probability that a memory error will alter the programmed logical behavior of the system
increases. A number of approaches have been taken to address this issue, but most involve Intellectual Property
(IP) cores that the user instantiates into the logic of their design, using valuable resources and possibly affecting
design performance. The MachXO2™ devices have a hardware implemented SED circuit which can be used to
detect SRAM errors and allow them to be corrected.
This document describes the hardware-based SRAM CRC Error Detect (SED) approach taken by Lattice Semicon-
ductor for MachXO2 PLDs.
SED Overview
The SED hardware in the MachXO2 devices is part of the Embedded Functional Block (EFB) consists of an access
point to the PLD's Configuration Logic, a Controller Circuit, and a 32-bit register to store the CRC for a given bit-
stream (see Figure 1). The SED hardware reads serial data from the PLD's Configuration memory and calculates a
CRC. The data that is read, and the CRC that is calculated, does not include EBR memory or PFUs used as RAM.
The calculated CRC is then compared with the expected CRC that was stored in the 32-bit register. If the CRC val-
ues match it indicates that there has been no configuration memory corruption, but if the values differ an error sig-
nal is generated.
Figure 1. System Block Diagram
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
Configuration Clock
Divider (66MHz)
Internal OSC
266MHz
SED Clock Divider
(2.08MHz - 33MHz)
MachXO2 SED Usage Guide
EFB
Glitchless
SMCLK
Clock
MUX
1
Technical Note TN1206
Configuration
Logic
SED Control
Circuit
32-Bit CRC
Register
TN1206_2.0

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Summary of Contents for Lattice Semiconductor MachXO2 Series

  • Page 1 Register © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 2: Sed Limitations

    MachXO2 SED Usage Guide Note that the calculated CRC is based on the particular arrangement of configuration memory for a particular design. Consequently, the expected CRC results cannot be specified until after the design is placed and routed. ® ® The Lattice Diamond or ispLEVER bitstream generation software analyzes the configuration of a placed and...

  • Page 3: Standard Sed

    MachXO2 SED Usage Guide Standard SED The Standard SED operation can be used by instantiating the SEDFA primitive which is shown in Figure 2. The primitive port definitions are listed in Table 1. See the Port Descriptions section of this document for more detailed information about each of the ports.

  • Page 4: Signal Descriptions

    MachXO2 SED Usage Guide Signal Descriptions Table 1. SEDFA Primitive Port Definitions Signal Name Direction Active Description SEDENABLE Input High SRAM CRC enable SEDSTART Input Rising Edge Start SRAM CRC cycle SEDFRCERR Input Rising Edge Force an SRAM CRC error flag SEDSTDBY Input High...
  • Page 5 MachXO2 SED Usage Guide Table 3. SED Attributes Attribute Name Attribute Type Description SED_CLK_FREQ String Specifies the clock frequency when used with SEDFA primitive. DEV_DENSITY String Specifies the device density for use by the simulation model. CHECKALWAYS String Reserved for future use. The SED_CLK_FREQ attribute is used to specify the clock frequency.
  • Page 6 MachXO2 SED Usage Guide SEDDONE SEDDONE is an output which indicates that SED checking has completed a cycle. This signal is an active high out- put from the SED hardware, clocked out on the rising edge of SEDCLKOUT. SEDDONE will be reset by a low SED- START signal.

  • Page 7: Timing Diagram For Sed Operation

    MachXO2 SED Usage Guide Timing Diagram for SED Operation Figure 5. Timing Diagram for SED Operation SEDENABLE EN_MIN ST_HMIN ST_LMIN SEDSTART IPDEL INPROG_TYP SEDINPROG FESETUP_MIN FEHOLD_MIN ERROUT OUT_CLR FE_MIN SEDFRCERR SEDERR DONE_SET SEDDONE Where: Parameter Value Units SEDCLK EN_MIN SEDCLK IPDEL SEDCLK FEHOLD_MIN...

  • Page 8: Sample Code

    MachXO2 SED Usage Guide Table 4. SED Run Time XO2- XO2- XO2- XO2- XO2- XO2- XO2- XO2- XO2- 640U 1200 1200U 2000 2000U 4000 7000 Density 191K 360K 360K 535K 535K 972K 972K 1534K Units 33.25 MHz 0.35 0.72 1.35 1.35 2.01 2.01...

  • Page 9: Sed Verilog Examples

    MachXO2 SED Usage Guide SEDSTDBY => sed_stdby, SEDERR => sed_err, SEDDONE => sed_done, SEDINPROG => sed_active, SEDCLKOUT => sed_clkout); SED Verilog Examples Verilog SEDFA module SEDFA (SEDENABLE, SEDSTART, SEDFRCERR, SEDSTDBY, SEDERR, SEDDONE, SEDINPROG, SEDCLKOUT); input SEDENABLE, SEDSTART, SEDFRCERR, SEDSTDBY; output SEDERR, SEDDONE, SEDINPROG, SEDCLKOUT;...

  • Page 10: Revision History

    MachXO2 SED Usage Guide Revision History Date Version Change Summary January 2017 Updated the SED Run Time section. Revised values in Table 4, SED Run Time. Updated the Technical Support Assistance section. Updated document template. December 2013 01.9 Updated the body text to match Timing Diagram for SED Operation. February 2013 01.8 Removed requirements for holding user logic in a steady state.

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