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Lattice Semiconductor MachXO2 User Manual

Lpddr sdram controller ip core
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MachXO2 LPDDR SDRAM Controller IP Core User's Guide
October 2012
IPUG92_01.2

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Summary of Contents for Lattice Semiconductor MachXO2

  • Page 1 MachXO2 LPDDR SDRAM Controller IP Core User’s Guide October 2012 IPUG92_01.2...

  • Page 2: Table Of Contents

    Number of Output Pins..........................19 © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 3 E-mail Support ............................30 Local Support ............................. 30 Internet ............................... 30 References................................30 JEDEC Web Site..............................30 Revision History ..............................31 Appendix A. Resource Utilization ....................... 32 MachXO2 Devices .............................. 32 Ordering Part Number............................32 IPUG92_01.2, October 2012 LPDDR SDRAM Controller User’s Guide...

  • Page 4: Chapter 1. Introduction

    LPDDR memory controller with the remainder of the application and minimizes the need to directly deal with the LPDDR memory interface. Quick Facts Table 1-1 gives quick facts about the LPDDR SDRAM Controller IP core for MachXO2™ devices. Table 1-1. LPDDR SDRAM Controller IP Core Quick Facts MachXO2 FPGA Family...

  • Page 5: Chapter 2. Functional Description

    Application Logic Block, Data Control Block and I/O Training Block. LPDDR I/O modules provide the PHY interface to the memory device. This block mostly consists of MachXO2 device I/O primitives supporting compli- ance to LPDDR electrical and timing requirements.

  • Page 6: I/O Training Block

    I/O Training Block The I/O Training Block adjusts the MachXO2 I/Os for write/read operations. It is automatically activated at the end of an initialization sequence and at the end of every auto refresh burst. It is an IPexpress GUI-programmable parameter.
  • Page 7 Functional Description Table 2-1. LPDDR SDRAM Memory Controller Top-Level I/O List for Generic Interface (Continued) Port Name Active State Description data_mask[(DSIZE/8)-1:0] Input Data mask input for write_data. System clock output. The user logic uses this as a system sclk Output clock unless an external clock generator is used.

  • Page 8: Using The Local User Interface

    Functional Description Table 2-2. LPDDR SDRAM Memory Controller Top-Level I/O List for Wishbone Interface (Continued) Port Name Description PORT0_DAT_O[31:0], Output The data Output array used for read data PORT1_DAT_O[31:0] PORT0_ACK_O, The acknowledge output ACK_O, when asserted, indicates the termination of Output PORT1_ACK_O a normal bus cycle by the slave...

  • Page 9: User Commands

    Functional Description the user logic that it is ready to receive a command by asserting the cmd_rdy signal for one cycle. If the core finds the cmd_valid signal asserted by the user logic while cmd_rdy is asserted, it takes the cmd input as a valid user command.
  • Page 10 Functional Description WRITE The user initiates a memory write operation by asserting cmd_valid along with the WRITE or WRITEA command and the address. After the WRITE command is accepted, the memory controller core asserts the datain_rdy signal when it is ready to receive the write data from the user logic to write into the memory. Since the duration from the time a write command is accepted to the time the datain_rdy signal is asserted is not fixed, the user logic needs to monitor the datain_rdy signal.

  • Page 11: Power Down And Deep Power Down

    Functional Description Figure 2-5. User-Side Read Operation Burst length = 2 Burst length = 4 read_data_valid read_data Burst length = 8 read_data_valid read_data READA READA is treated in the same way as a READ command except that the core issues a Read with Auto Precharge command to the memory instead of a READ command.

  • Page 12: Local-To-Memory Address Mapping

    Functional Description The memory command mapping of the port_1 wishbone bus are described in Table 2-5. Table 2-5. Memory Command Mapping of the port_1 Wishbone Bus PORT1_ADDR_I PORT1_DATA_I Command Description Bits [B2,B1,B0] = Burst length Bits [B3] = Burst type 32‘h1 Bits [B6,B5,B4] = CAS latency Valid data =[B6, …...

  • Page 13: Mode Register Programming

    Functional Description Mode Register Programming The LPDDR SDRAM memory devices are programmed using the mode registers MRS and EMRS. The bank address bus (em_ddr_ba) is used to choose one of the Mode registers, while the programming data is delivered through the address bus (em_ddr_addr). The memory data bus cannot be used for mode register programming. The Lattice LPDDR memory controller core uses the local address bus, addr, to program these registers.

  • Page 14: Chapter 3. Parameter Settings

    SDRAM Controller IP core Configuration GUI in IPexpress. Table 3-1. LPDDR Core Configuration Parameters Configuration Parameter Configuration 1 Configuration 2 Configuration 3 Configuration 4 Design Entry Verilog HDL Device Family MachXO2 Part Name LCMXO2-7000HE-6BG256C Memory Micron MT46H64M16LF Clock 133 MHz Data Width Wishbone Disable Disable...

  • Page 15: Type Tab

    Parameter Settings Figure 3-1. Mode Options in the IPexpress Tool Type Tab The Type tab allows the user to select the LPDDR controller configuration for the target memory device and the core functional features. These parameters are considered as static parameters since the values for these param- eters can only be set in the GUI.

  • Page 16: Clock

    LCMXO2-7000HC-6BG256CES. Memory Data Bus Size The MachXO2 device family provides a 16-bit I/O interface to the LPDDR memory. Data_rdy to Write Data Delay User logic is allowed to send the write data to the controller after a one-clock cycle delay with respect to the datain_rdy signal.

  • Page 17: I/O Auto Training

    Parameter Settings I/O Auto Training This is an on/off option and if enabled, the controller will train the I/Os automatically. Refer to “I/O Training” on page for more information. Periodic I/O Auto Retraining This is an on/off option and if enabled, the controller will auto retrain the I/Os at the end of every refresh burst auto- matically.

  • Page 18: Memory Device Timing Tab

    Parameter Settings Memory Device Timing Tab Figure 3-4 shows the contents of the Memory Device Timing tab. Figure 3-4. Memory Device Timing Options in the IPexpress Tool The default memory timing parameters displayed in this tab are the default values of the Micron Technology LPDDR 1Gb module.

  • Page 19: Support Synplify

    Parameter Settings Support Synplify If selected, IPexpress generates evaluation scripts and other associated files required to synthesize the top-level design using the Synopsys Synplify synthesis tool. Support ModelSim If selected, IPexpress generates evaluation script and other associated files required to synthesize the top-level design using the Mentor Graphics ModelSim simulator.

  • Page 20: Getting Started

    The LPDDR SDRAM IP core can be used in the MachXO2 device family. For example information and known issues on this IP core see the Lattice LPDDR IP ReadMe document. This file is available once the core is installed in Diamond.
  • Page 21 IP Core Generation Figure 4-1. IPexpress Dialog Box Note that if the IPexpress tool is called from within an existing project, Project Path, Design Entry, Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool online help for further infor- mation.

  • Page 22: Ipexpress-Created Files And Top Level Directory Structure

    When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are generated in the specified Project Path directory. The directory structure of the generated files is shown in Figure 4- Figure 4-3. MachXO2 LPDDR Core Directory Structure LPDDR SDRAM Controller IP Core File Structure Table 4-1 provides a list of key files and directories created by the IPexpress tool and how they are used.

  • Page 23: Top-Level Wrapper

    IP Core Generation Table 4-1. File List (Continued) File Description This file provides a module which instantiates the LPDDR SDRAM core. This file can be easily <username>_top.[v,vhd] modified for the user's instance of the LPDDR SDRAM core. This file is located in the lpddr_eval/<username>/src directory.

  • Page 24: Simulation Files For Ip Core Evaluation

    IP Core Generation Simulation Files for IP Core Evaluation Once a LPDDR SDRAM Controller IP core is generated, it contains a complete set of test bench files to simulate a few example core activities for evaluation. The simulation environment for the LPDDR memory controller IP is shown in Figure 4-5.

  • Page 25: Evaluation Script File

    IP Core Generation Evaluation Script File ModelSim and Aldec Active-HDL simulation macro script files are included for instant evaluation of the IP core. All required files for simulation are included in the macro script. This simulation script can be used as a starting point of a user simulation project.

  • Page 26: Hardware Evaluation

    IP Core Generation supports the ability to implement the LPDDR SDRAMlpddr_eval core in isolation. Push-button implementation of this top-level design with Synplify RTL Synthesis is supported via the project files <username>_eval.ldf located in the \<project_dir>\lpddr_eval\<username>\impl\synplify directory. To use this project file: 1.
  • Page 27 IP Core Generation 8. Click Generate. 9. Check the Generate Log tab to check for warnings and error messages. 10.Click Close. The IPexpress package file (.ipx) supported by Diamond holds references to all of the elements of the generated IP core required to support simulation, synthesis and implementation.

  • Page 28: Chapter 5. Application Support

    • IOBUF – The IOBUF preference assigns the required I/O types to the LPDDR I/O pads. • LOCATE – For all MachXO2 devices the memory data and data strobe pins are located at the right side of the device. For this reason these I/Os are grouped and locked to Bank 1.

  • Page 29: Chapter 6. Core Verification

    Chapter 6: Core Verification The functionality of the MachXO2 LPDDR SDRAM Controller IP core has been verified via simulation with LPDDR simulation models from Micron Technology, including: • Simulation environment verifying proper LPDDR functionality using Lattice’s proprietary verification environment. IPUG92_01.2, October 2012...

  • Page 30: Chapter 7. Support Resources

    Local Support Contact your nearest Lattice sales office. Internet www.latticesemi.com References • DS1035, MachXO2 Family Data Sheet JEDEC Web Site The JEDEC website contains specifications and documents referred to in this user's guide. The JEDEC URL is: www.jedec.org. IPUG92_01.2, October 2012...

  • Page 31: Revision History

    Initial release. December 2011 01.1 Updated Quick Facts table. Updated LPDDR Core Configuration Parameters table. Appendix A – Updated Performance and Resource Utilization table for MachXO2. ® Removed references to ispLEVER design software. October 2012 01.2 Updated document with new corporate logo.

  • Page 32: Appendix A. Resource Utilization

    1. Performance and utilization data are generated using a LCMXO2-7000HE-6BG256C device in Lattice Diamond 1.3 design software. Per- formance may vary when using this IP core in a different density, speed or grade within the MachXO2 family. 2. SDRAM data path width of 16 bits.

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