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Manuals and User Guides for NEC PD754244. We have
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NEC PD754244 manual available for free PDF download: User Manual
NEC PD754244 User Manual (306 pages)
4-Bit Single-Chip Microcontrollers
Brand:
NEC
| Category:
Computer Hardware
| Size: 1.89 MB
Table of Contents
Table of Contents
9
Chapter 1 General
17
Functional Outline
18
Ordering Information
19
Differences between Series Products
19
Block Diagram
20
Pin Configuration (Top View)
21
Chapter 2 Pin Functions
24
Pin Functions of Μ PD754244
24
Pin Functions of Digital I/O Ports
24
Functions of Non-Port Pins
25
Description of Pin Functions
26
P30 to P33 (Port 3), P60 to P63 (Port 6), P80 (Port 8)
26
P70 to P73 (Port 7)
26
PTO0 to PTO2
26
Int0
27
KR4 to KR7
27
Krren
27
TH00 and TH01
27
CL1 and CL2 ( Μ PD754144 Only)
28
Ref
28
Reset
28
X1 and X2 ( Μ PD754244 Only)
28
Vss
29
Pin I/O Circuits
30
VDD
30
Av Ref
31
Processing of Unused Pins
31
Recommended Connection of Unused Pins
31
Chapter 3 Features of Architecture and Memory Map
32
Bank Configuration of Data Memory and Addressing Modes
32
Bank Configuration of Data Memory
32
Selecting MBE = 0 Mode and MBE = 1 Mode
33
Addressing Mode of Data Memory
34
Data Memory Configuration and Addressing Range for each Addressing Mode
35
Addressing Modes
36
Updating Address of Static RAM
39
Bank Configuration of General-Purpose Registers
45
Example of Using Different Register Banks for Normal Routine and Interrupt Routine
45
Register Bank Selected by RBE and RBS
45
Example of Using Register Banks
46
Configuration of General-Purpose Registers (4-Bit Processing)
48
Configuration of General-Purpose Registers (8-Bit Processing)
49
Memory-Mapped I/O
50
Addressing Modes Applicable to Peripheral Hardware Unit Manipulation
50
Μ PD754244 I/O Map
52
Chapter 4 Internal Cpu Function
60
Function to Select Mki and Mkii Modes
60
Difference between Mki and Mkii Modes
60
Differences between Mki and Mkii Modes
60
Setting Stack Bank Select Register (SBS)
61
Format of Stack Bank Select Register
61
Program Counter (PC)
62
Configuration of Program Counter
62
Program Memory (ROM)
63
Program Memory Map
64
Data Memory (RAM)
65
Configuration of Data Memory
65
Specifying Bank of Data Memory
66
Data Memory Map
67
General-Purpose Registers
69
Configuration of General-Purpose Register Area
69
Configuration of Register Pair
69
Accumulator
70
Stack Area Selected by SBS
70
Stack Pointer (SP) and Stack Bank Select Register (SBS)
70
Stack Pointer and Stack Bank Selection Register Configuration
71
Data Restored from Stack Memory (Mki Mode)
72
Data Saved to Stack Memory (Mki Mode)
72
Data Restored from Stack Memory (Mkii Mode)
73
Program Status Word (PSW)
74
Data Saved to Stack Memory (Mkii Mode)
73
Configuration of Program Status Word
74
PSW Flags Saved/Restored To/From Stack
74
Carry Flag Manipulation Instruction
75
Contents of Interrupt Status Flags
76
Bank Select Register (BS)
78
Configuration of Bank Select Register
78
MBE, MBS, and Memory Bank Selected
78
RBE, RBS, and Register Bank Selected
79
Chapter 5 Eeprom
80
EEPROM Configuration
80
EEPROM Features
80
EEPROM Write Control Register (EWC)
81
Format of EEPROM Write Control Register
81
Interrupt Related to EEPROM Control
82
EEPROM Manipulation Method
83
EEPROM Manipulation Instructions
83
Read Manipulation
84
EEPROM Write Control Register in EEPROM Read Manipulation
84
Write Manipulation
85
EEPROM Write Control Register in EEPROM Write Manipulation
85
Cautions on EEPROM Writing
87
Chapter 6 Peripheral Hardware Function
88
Digital I/O Ports
88
Data Memory Address of Digital Ports
88
Types, Features, and Configurations of Digital I/O Ports
89
Types and Features of Digital Ports
89
P3N Configuration (N = 0 to 2)
90
P33 Configuration
90
P60 Configuration
91
P61 Configuration
91
P62 Configuration
92
P63 Configuration
92
P7N Configuration (N = 0 to 3)
93
P80 Configuration
93
Setting I/O Mode
94
Format of each Port Mode Register
95
Digital I/O Port Manipulation Instruction
96
I/O Pin Manipulation Instructions
97
Operation of Digital I/O Port
98
Operation When I/O Port Is Manipulated
99
Connecting Pull-Up Resistor
100
Format of Pull-Up Resistor Specification Register
100
Specifying Connection of Pull-Up Resistor
100
I/O Timing of Digital I/O Port
101
ON Timing of Internal Pull-Up Resistor Connected Via Software
102
Clock Generator
103
Block Diagram of Clock Generator
103
Configuration of Clock Generator
103
Function and Operation of Clock Generator
105
Format of Processor Clock Control Register
107
Crystal/Ceramic Oscillation External Circuit
108
RC Oscillation External Circuit
108
Example of Incorrect Resonator Connection
109
Setting CPU Clock
112
Maximum Time Required for CPU Clock Switching
112
CPU Clock Switching Example
113
Basic Interval Timer/Watchdog Timer
114
Block Diagram of Basic Interval Timer/Watchdog Timer
114
Configuration of Basic Interval Timer/Watchdog Timer
114
Basic Interval Timer Mode Register (BTM)
115
Format of Basic Interval Timer Mode Register
116
Watchdog Timer Enable Flag (WDTM)
117
Format of Watchdog Timer Enable Flag (WDTM)
117
Operation as Basic Interval Timer
118
Operation as Watchdog Timer
119
Other Functions
121
Timer Counter
122
Configuration of Timer Counter
122
Mode List
122
Format of Timer Counter Mode Register (Channel 0)
127
Format of Timer Counter Mode Register (Channel 1)
128
Format of Timer Counter Mode Register (Channel 2)
130
Format of Timer Counter Output Enable Flag
132
Format of Timer Counter Control Register
133
Operation in 8-Bit Timer Counter Mode
134
Setting of Timer Counter Mode Register
135
Setting of Timer Counter Control Register
138
Setting of Timer Counter Output Enable Flag
138
Resolution and Longest Set Time (8-Bit Timer Counter Mode)
139
Configuration When Timer Counter Operates
143
Count Operation Timing
143
Operation in PWM Pulse Generator Mode (PWM Mode)
145
Setting of Timer Counter Mode Register
146
Setting of Timer Counter Control Register
147
PWM Pulse Generator Operating Configuration
149
PWM Pulse Generator Operating Timing
149
Operation in 16-Bit Timer Counter Mode
151
Setting of Timer Counter Mode Registers
152
Setting of Timer Counter Control Register
153
Resolution and Longest Set Time (16-Bit Timer Counter Mode)
154
Configuration When Timer Counter Operates
157
Timing of Count Operation
158
Operation in Carrier Generator Mode (CG Mode)
160
Setting of Timer Counter Mode Register (N = 1, 2)
161
Setting of Timer Counter Control Register
162
Setting of Timer Counter Output Enable Flag
162
Configuration in Carrier Generator Mode
165
Carrier Generator Operation Timing
166
Notes on Using Timer Counter
173
Programmable Threshold Port (Analog Input Port)
180
Configuration and Operation of Programmable Threshold Port
180
Block Diagram of Programmable Threshold Port
181
Programmable Threshold Port Mode (PTHM) Register
182
Programmable Threshold Port Application
183
Application Example of Programmable Threshold Port
183
Bit Sequential Buffer
184
Format of Bit Sequential Buffer
184
Chapter 7 Interrupt and Test Functions
186
Configuration of Interrupt Controller
186
Types of Interrupt Sources and Vector Table
188
Interrupt Vector Table
189
Hardware Controlling Interrupt Function
190
Signals Setting Interrupt Request Flags
191
Interrupt Priority Select Register
192
Configuration of INT0
194
I/O Timing of Noise Eliminator
194
Format of INT0 Edge Detection Mode Register (IM0)
195
IST1 and IST0 and Interrupt Servicing Status
196
Interrupt Sequence
197
Interrupt Servicing Sequence
197
Nesting Control of Interrupts
198
Nesting of Interrupt with High Priority
198
Interrupt Nesting by Changing Interrupt Status Flag
199
Servicing of Interrupts Sharing Vector Address
200
Identifying Interrupt Sharing Vector Address
200
Machine Cycles until Interrupt Servicing
202
Effective Usage of Interrupts
204
Application of Interrupt
204
Test Function
212
Types of Test Sources
212
Hardware Controlling Test Function
212
Test Request Flag Setting Signals
212
Block Diagram of KR4 to KR7
213
Format of INT2 Edge Detection Mode Register (IM2)
214
KR4 to KR7 Pins, KRREN Pin and Test Function
214
Chapter 8 Standby Function
215
Settings and Operating Statuses of Standby Mode
216
Operating Statuses in Standby Mode
216
Block Diagram of Interrupt Controller
217
Releasing Standby Mode
218
Selecting Wait Time by BTM
220
Wait Time after Releasing STOP Mode
220
STOP Mode Release by Key Return Reset or RESET Input
221
Operation after Release of Standby Mode
222
Application of Standby Mode
222
Chapter 9 Reset Function
227
Configuration and Operation of Reset Function
227
Configuration of Reset Circuit
227
Reset Operation by RESET Signal
228
Status of each Hardware Unit after Reset
229
Watchdog Flag (WDF), Key Return Flag (KRF)
231
WDF and KRF Contents Corresponding to each Signal
231
WDF Operation in Generating each Signal
231
KRF Operation in Generating each Signal
232
Chapter 10 Mask Options
233
Pin Mask Options
233
Mask Option of P70/KR4 to
233
RESET Pin Mask Option
233
Oscillation Stabilization Wait Time Mask Option
233
Selection of Mask Options
233
Chapter 11 Instruction Set
234
Unique Instructions
234
GETI Instruction
234
Bit Manipulation Instruction
235
String-Effect Instruction
235
Types of Bit Manipulation Addressing Modes and Specification Range
235
Base Number Adjustment Instruction
236
Skip Instruction and Number of Machine Cycles Required for Skipping
237
Instruction Set and Operation
237
Opcode of each Instruction
248
Instruction Function and Application
254
Transfer Instructions
255
Table Reference Instructions
261
Bit Transfer Instructions
265
Operation Instructions
266
Accumulator Manipulation Instructions
272
Increment/Decrement Instructions
273
Compare Instructions
274
Carry Flag Manipulation Instructions
275
Memory Bit Manipulation Instructions
276
Branch Instructions
279
Subroutine/Stack Control Instructions
283
Interrupt Control Instructions
287
Input/Output Instructions
288
CPU Control Instruction
289
Special Instructions
290
Appendix A Development Tools
293
Appendix B Ordering Mask Rom
297
Appendix C Instruction Index
298
Instruction Index (by Function)
298
C.1 Instruction Index (by Function)
298
Instruction Index (Alphabetical Order)
301
Appendix D Hardware Index
304
Appendix E Revision History
306
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