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RM-298; RM-299
System Module
From the antenna, the received RF-signal is fed into the front-end module, which routes the signal to the
appropriate RX path. After the FEM, the RX signals are filtered by SAW filters (one for each band), which reject
the out-of band blocking signals to low enough level to be handled by the RF ASIC.
There are two paths – one for each band. In each path, the signal is then fed to the low noise amplifier (LNA).
One LNA can handle both the GSM850 and GSM900 signals and another is used for GSM1800 and GSM1900.
The LNA inputs are matched to the SAW filter outputs by means of discrete LC matching networks. The SAW
filters and the matching networks are different for different band combinations, but the PWB layout is the
same for both 850/1900 and 900/1800 versions.
The RX front-end circuitry contains the LNA and the quadrature down converting mixers. The front-end gain
is programmable so that the gain can be reduced in strong-signal conditions. The mixers at each signal path
convert the RF signal directly down to baseband I/Q signals. Local oscillator signals for the mixers are
generated by an on-chip VCO.
The output signals (I/Q) of each demodulator are all differential. They are combined to two differential signal
paths, one for I-channel and one for Q-channel, common for all bands. The baseband RX signals are then fed
into a 3rd order active blocking filter, which has programmable gain. One of the three poles is implemented
by an off-chip capacitor connected directly between the mixer outputs. There are a total of two off-chip
capacitors, one for I-channel and one for Q-channel, respectively.
After the blocking filter, the signal is fed into a buffer amplifier, which also has programmable gain. Around
the amplifier there is the first DC-offset compensation block, which removes most of the cumulated DC offset
so far. The DC offset compensation method is based on digital successive approximation technique.
The next block in the RX chain is a switched-capacitor (SC) channel filter, which provides the close-in selectivity
for the analog receiver. Because the SC-filter is insensitive to the IC process tolerances, no production
calibration of the filter is necessary. The SC-filter operates on 6.5 MHz clock, which is generated by dividing
the 26 MHz reference clock by four.
After the SC-filter there is a continuous-time smoothing filter which attenuates the alias signals generated
by the sampling process inherent in the SC-filter. The smoothing filter also has programmable gain.
The next block is a programmable gain amplifier (PGA), which has the second DC-offset compensation block
around it. The DC-offset compensation method is again based on digital successive approximation technique.
The last block in the analog receiver is an output buffer amplifier, which feeds the differential I/Q signals off-
chip to be A/D converted in the digital baseband.
VCXO and PLL
The VCO frequency is locked by a PLL (phase locked loop) into a stable frequency source given by a VCXO. The
frequency of the VCXO is in turn locked into the frequency of the base station with the help of an AFC (automatic
frequency control) voltage, which is generated in the UEM. The reference frequency is 26 MHz.
The VCXO also provides a 26 MHz system clock for the digital baseband.
The PLL is located in PMB3258 and it is controlled via the RFBUS.
Page 6 –22
COMPANY CONFIDENTIAL
Issue 1
Copyright © 2007 Nokia. All rights reserved.
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