Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
Page 2 MVME2400 Series VME Processor Module Programmer’s Reference Guide V2400A/PG2 August 2000 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 3 © Copyright 2000 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola and the Motorola symbol are registered trademarks of Motorola, Inc. ® Motorola and the Motorola symbol are registered trademarks of Motorola, Inc. PowerStack , VMEmodule , and VMEsystem are trademarks of Motorola, Inc.
Page 4: Safety Summary
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
Page 5 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
Page 6 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Page 7 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
Page 8: Table Of Contents
Contents About This Manual Summary of Changes ....................vii Overview of Contents ....................viii Comments and Suggestions ..................viii Manual Terminology....................ix Conventions Used in This Manual................xi CHAPTER 1 Board Description and Memory Maps Introduction........................1-1 Overview........................1-1 Feature Summary .......................1-2 System Block Diagram ....................1-3 Functional Description....................1-5 Overview......................1-5 Programming Model ....................1-6...
Page 9 ISA DMA Channels ..................1-34 CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Introduction ....................... 2-1 Overview ......................2-1 Features ......................2-1 Block Diagram......................2-3 Functional Description ....................2-4 Architectural Overview ..................2-4 PPC Bus Interface ....................2-5 PPC Address Mapping ................
Page 10 Nesting of Interrupt Events................2-53 Spurious Vector Generation ................2-53 Interprocessor Interrupts (IPI) ................2-53 8259 Compatibility ...................2-54 PHB Detected Errors ..................2-54 Timers .......................2-55 Interrupt Delivery Modes..................2-55 Block Diagram Description ................2-56 Program Visible Registers .................2-58 Interrupt Pending Register (IPR) ...............2-58 Interrupt Selector (IS) ................2-58 Interrupt Request Register (IRR)...............2-59 In-Service Register (ISR) ................2-59 Interrupt Router ..................2-59...
Page 11 WDTxCNTL Registers ................2-88 WDTxSTAT Registers................2-90 General Purpose Registers ................ 2-90 PCI Registers ....................2-91 Vendor ID/ Device ID Registers ............... 2-92 PCI Command/ Status Registers ............... 2-93 Revision ID/ Class Code Registers ............2-95 Header Type Register................2-95 MPIC I/O Base Address Register .............
Page 12 Block Diagrams ......................3-2 Functional Description....................3-6 Performance ......................3-6 Four-beat Reads/Writes ................3-6 Single-beat Reads/Writes ................3-7 Address Pipelining..................3-7 Page Holding ....................3-7 SDRAM Speeds...................3-7 SDRAM Organization .................3-9 ROM/Flash Speeds ..................3-10 PowerPC 60x Bus Interface................3-12 Responding to Address Transfers..............3-12 Completing Data Transfers................3-13 PPC60x Data Parity ...................3-13 PPC60x Address Parity ................3-13 Cache Coherency ..................3-14 Cache Coherency Restrictions..............3-14...
Page 13 CLK Frequency Register................3-44 ECC Control Register ................3-45 Error Logger Register ................3-49 Error_Address Register ................3-50 Scrub/Refresh Register................3-51 Scrub Address Register ................3-52 ROM A Base/Size Register............... 3-53 ROM B Base/Size Register ............... 3-56 ROM Speed Attributes Registers .............. 3-58 Data Parity Error Log Register ..............
Page 14 Product Overview - Features ................4-1 Functional Description....................4-2 Architectural Overview..................4-2 VMEbus Interface..................4-4 PCI Bus Interface..................4-5 Interrupter and Interrupt Handler ..............4-6 DMA Controller ..................4-7 Registers - Universe II Control and Status Registers (UCSR) ........4-8 Universe II Register Map..................4-9 CHAPTER 5 Programming Details Introduction........................5-1 PCI Arbitration......................5-1 Interrupt Handling......................5-2...
Page 15 Example VPD SROM ..................A-9 APPENDIX B Related Documentation Motorola Computer Group Documents ..............B-1 Manufacturers’ Documents ..................B-1 Related Specifications ....................B-4 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 16 List of Figures Figure 1-1. MVME2400 Series System Block Diagram ...........1-4 Figure 1-2. VMEbus Master Mapping..............1-19 Figure 1-3. VMEbus Slave Mapping ...............1-21 Figure 1-4. General-Purpose Software-Readable Header........1-26 Figure 2-1. Hawk’s PCI Host Bridge Block Diagram ..........2-3 Figure 2-2. PPC to PCI Address Decoding..............2-6 Figure 2-3.
Page 17 List of Tables Table 1-1. MVME240x Features................1-2 Table 1-2. Default Processor Memory Map...............1-6 Table 1-3. CHRP Memory Map Example..............1-7 Table 1-4. PHB Register Values for CHRP Memory Map ........1-9 Table 1-5. PREP Memory Map Example..............1-10 Table 1-6. PHB Register Values for PREP Memory Map ........1-11 Table 1-7.
Page 18 Table 2-16. PPC Register Map for PHB..............2-66 Table 2-17. PCI Configuration Register Map............2-91 Table 2-18. PCI I/O Register Map................2-92 Table 2-19. MPIC Register Map................2-105 Table 2-20. Cascade Mode Encoding ..............2-109 Table 2-21. Tie Mode Encoding ................2-109 Table 3-1.
Page 19 Table A-3. FLASH Memory Configuration Data ............A-5 Table A-4. L2 Cache Configuration Data ..............A-6 Table A-5. VPD SROM Configuration Specification for 01-W3394F01* .....A-9 Table B-1. Motorola Computer Group Documents ..........B-1 Table B-2. Manufacturers’ Documents ..............B-2 Table B-3. Related Specifications ................B-5...
Page 20: About This Manual
Guide provides brief board level information, complete memory maps, and detailed ASIC chip information including register bit descriptions for the MVME2400 series VME Processor Modules (also called MVME240x in this manual). The information contained in this manual applies to the single board computers built from some of the plug-together components listed in the following table.
Page 21: Overview Of Contents
Documentation, includes all documentation related to the MVME240x. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:...
Page 22: Manual Terminology
You can also submit comments to the following e-mail address: reader-comments@mcg.mot.com In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.
Page 23 Chapter 5, Programming Details Endian Issues, which covers which parts of the MVME2400 series use big-endian byte ordering, and which use small-endian byte ordering. The terms control bit and status bit are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control.
Page 24: Conventions Used In This Manual
Conventions Used in This Manual The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories, and files.
Page 25: Introduction
1Board Description and Memory Maps Introduction This manual provides programming information for the MVME240x VME Processor Modules. Extensive programming information is provided for the primary Application-Specific Integrated Circuit (ASIC) devices used on the boards: the Hawk and Universe II chips. Reference information is included in Appendix B, Related Documentation for the...
Page 26: Feature Summary
Board Description and Memory Maps Feature Summary There are many models based on the MVME2400 series architecture. The following table summarizes the major features of the MVME2400 series: Table 1-1. MVME240x Features Feature Description Microprocessor 233 MHZ MPC750 PowerPC processor...
Page 27: System Block Diagram
Standard I/O functions are provided by the UART device which resides on the ISA bus. The NVRAM/RTC also resides on the ISA bus. The general system block diagram for MVME2400 series is shown below: http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 28: Figure 1-1. Mvme2400 Series System Block Diagram
Registers Buffers RTC/NVRAM/WD M48T59 TL16C550 UART VME P2 VME P1 2067 9708 2067 9708 Figure 1-1. MVME2400 Series System Block Diagram Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 29: Functional Description
ISA bus are: one asynchronous serial port, a real-time clock, counters/timers, and a software-readable header. The MVME2400 series board interfaces to the VMEbus via the P1 and P2 connectors, which use the 5-row 160-pin connectors as specified in the proposed VME64 Extension Standard. It also draws +5V, +12V, and -12V power from the VMEbus backplane through these two connectors.
Page 30: Programming Model
Board Description and Memory Maps Programming Model Memory Maps The following sections describe the memory maps for the MVME2400 series. Processor Memory Maps The Processor memory map is controlled by the Hawk ASIC. The Hawk ASIC has flexible programming Map Decoder registers to customize the system to fit many different applications.
Page 31: Table 1-3. Chrp Memory Map Example
(mapped to 00000000 to 007FFFFF) FE80 0000 FEF7 FFFF 7.5M Reserved FEF8 0000 FEF8 FFFF SMC Registers FEF9 0000 FEFE FFFF 384K Reserved FEFF 0000 FEFF FFFF PHB Registers http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 32 FFFF FFFF ROM/FLASH Bank A or Bank B Notes 1. Programmable via the Hawk ASIC. For the MVME2400 series, RAM size is limited to 256MB and ROM/FLASH to 9MB. 2. To enable the “Processor-hole” area, program the SMC to ignore 0x000A0000 - 0x000BFFFF address range and program the PHB to map this address range to PCI memory space.
Page 33: Table 1-4. Phb Register Values For Chrp Memory Map
0300 00C2 FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 & MSATT2 0000 0002 FEFF 0058 MSADD3 FE00 FE7F FEFF 005C MSOFF3 & MSATT3 0200 00C0 http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 34: Table 1-5. Prep Memory Map Example
FFFF FFFF ROM/FLASH Bank A or Bank B Notes 1. Programmable via the SMC. For the MVME2400 series, RAM size is limited to 256MB and ROM/FLASH to 9MB. 2. Programmable via the Hawk’s PHB. 3. The actual size of each ROM/FLASH bank may vary.
Page 35: Table 1-6. Phb Register Values For Prep Memory Map
CONFIG_ADD and CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC, respectively. With the PREP memory map, the CONFIG_ADD register and the CONFIG_DAT register are located at 0x80000CF8 and 0x80000CFC, respectively. http://www.motorola.com/computer/literature 1-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 36: Pci Memory Maps
Software must program the appropriate map decoders for a specific environment. PCI CHRP Memory Map The following table shows a PCI memory map of the MVME2400 series that is CHRP-compatible from the point of view of the PCI local bus. Table 1-7. PCI CHRP Memory Map...
Page 37: Table 1-8. Phb Pci Register Values For Chrp Memory Map
Reserved Notes 1. Programmable via the PHB’s PCI Configuration registers. For the MVME2400 series, RAM size is limited to 256MB. 2. To enable the CHRP “io-hole”, program the PHB to ignore the 0x000A0000 - 0x000FFFFF address range. 3. Programmable mapping via the four PCI Slave Images in the Universe II ASIC.
Page 38: Table 1-9. Universe Ii Pci Register Values For Chrp Memory Map
Board Description and Memory Maps Table 1-8. PHB PCI Register Values for CHRP Memory Map (Continued) Configuration Configuration Register Value Register Value Address Offset Register Name (Aliasing OFF) (Aliasing ON) PSOFF1 & PSATT1 0000 0000 0000 00FX PSADD2 0000 0000 0000 0000 PSOFF2 &...
Page 39: Table 1-10. Pci Prep Memory Map
$188 SLSI C0A053F8 PCI PREP Memory Map The following table shows a PCI memory map of the MVME2400 series that is PREP-compatible from the point of view of the PCI local bus. Table 1-10. PCI PREP Memory Map PCI Address...
Page 40: Table 1-11. Phb Pci Register Values For Prep Memory Map
PCI Memory Space Notes 1. Programmable via the PHB’s PCI Configuration registers. For the MVME2400 series, RAM size is limited to 256MB. 2. To enabled the CHRP “io-hole”, program the PHB to ignore the 0x000A0000 - 0x000FFFFF address range. 3. Programmable mapping via the four PCI Slave Images in the Universe II ASIC.
Page 41: Table 1-12. Universe Ii Pci Register Values For Prep Memory Map
3800 0000 $120 LSI1_TO XXXX 0000 $128 LSI2_CTL 0000 0000 $12C LSI2_BS XXXX XXXX $130 LSI2_BD XXXX XXXX $134 LSI2_TO XXXX XXXX $13C LSI3_CTL 0000 0000 http://www.motorola.com/computer/literature 1-17 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 42: Vmebus Mapping
C0A05338 VMEbus Mapping Note For the MVME2400 series, RAM size is limited to 256MB. VMEbus Master Map The processor can access any address range in the VMEbus with the help from the address translation capabilities of the Universe II ASIC. The...
Page 43: Figure 1-2. Vmebus Master Mapping
VME A16 NOTE 1 VME A24 PCI/ISA MEMORY SPACE VME A16 VME A24 I/O SPACE VME A16 RESOURCES 11553.00 9609 Figure 1-2. VMEbus Master Mapping http://www.motorola.com/computer/literature 1-19 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 44 Board Description and Memory Maps Notes 1. Programmable mapping done by the Hawk ASIC. 2. Programmable mapping via the four PCI Slave Images in the Universe II ASIC. 3. Programmable mapping via the Special Slave Image (SLSI) in the Universe II ASIC. VMEbus Slave Map The eight programmable VME Slave Images in the Universe II ASIC allow other VMEbus masters to get to any devices on the MVME2400...
Page 45: Figure 1-3. Vmebus Slave Mapping
1. Programmable mapping via the four VME Slave Images in the Universe II ASIC. 2. Programmable mapping via PCI Slave Images in the Hawk ASIC. 3. Fixed mapping via the PIB device. http://www.motorola.com/computer/literature 1-21 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 46: Table 1-13. Universe Ii Pci Register Values For Vmebus Slave Map Example
Board Description and Memory Maps The following table shows the programmed values for the associated Universe II registers for the VMEbus slave function. Table 1-13. Universe II PCI Register Values for VMEbus Slave Map Example Configuration Configuration Register Value Register Value Address Offset Register Name (CHRP)
Page 47: System Configuration Information
Vital product data contains static board build information that is typcially used for board initialization, configuration, and verification. Each board has its own unique VPD SROM containing local hardware configuration information. http://www.motorola.com/computer/literature 1-23 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 48 Board Description and Memory Maps The VPD consists of a header section, followed by contiguous formatted data packets. The header section consists of eye-catcher and size fields, and the data packets consist of identifier, data length, and data content fields. The header section begins with an eye-catcher field that can be used to verify the existence of an initialized VPD SROM (an optional EEPROM CRC packet may also be used to verify the integrity of the VPD content).
Page 49: Isa Local Resource Bus
PCI bus. Refer to the W83C553 Data Sheet for details. UART A 16550-compatible UART provides the MVME2400 series with an asynchronous serial port. Refer to the TL16C550 Data Sheet for additional details and programming information.
Page 50: General-Purpose Software-Readable Header (Srh) Switch (S3)
SRH Register Bit 7 is associated with Pin 8 and Pin 9 of the SRH. The SRH is a read-only register. If Motorola’s PowerPC firmware, PPCBug, is being used, it reserves all bits, SRH0 to SRH7. If it is not being used, the switch can be used for other applications.
Page 51: Vme Registers
Slave Image 0 into the appropriate PCI I/O address range. Refer to the VMEbus Slave Map section for additional details. The following table shows the registers provided for various VME functions: http://www.motorola.com/computer/literature 1-27 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 52: Lm/Sig Control Register
Board Description and Memory Maps Table 1-17. VME Registers PCI I/O Address Function 0000 1000 LM/SIG Control Register 0000 1001 LM/SIG Status Register 0000 1002 VMEbus Location Monitor Upper Base Address 0000 1003 VMEbus Location Monitor Lower Base Address 0000 1004 VMEbus Semaphore Register 1 0000 1005 VMEbus Semaphore Register 2...
Page 53: Lm/Sig Status Register
LM1 bit is asserted. EN_LM0 When the EN_LM0 bit is set, a LM/SIG Interrupt 0 is generated and the LM0 bit is asserted. http://www.motorola.com/computer/literature 1-29 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 54: Location Monitor Upper Base Address Register
Board Description and Memory Maps SIG1 SIG1 status bit. This bit can only be set by the SET_LM1 control bit. It can only be cleared by a reset or by writing a 1 to the CLR_LM1 control bit. SIG0 SIG0 status bit. This bit can only be set by the SET_LM0 control bit.
Page 55: Location Monitor Lower Base Address Register
Semaphore Register 1 - Offset $1004 FIELD SEM1 OPER RESET http://www.motorola.com/computer/literature 1-31 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 56: Semaphore Register 2
RESET Emulated Z8536 CIO Registers and Port Pins Although the MVME2400 series does not use a Z8536, there are several functions within this part that are emulated within an ISA Register PLD. These functions are accessed by reading/writing the Port A, B, C Data Registers and Control Register.
Page 57: Z8536 Cio Port Pins
Not used BRDFAIL Output Board Fail: When set will cause BFL LED to be lit. Not used Not used Not used Not used Not used http://www.motorola.com/computer/literature 1-33 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 58: Isa Dma Channels
01b = MVME1600-011 10b = Reserved 11b = MVME1600-001 ISA DMA Channels The MVME2400 series does not implement any ISA DMA channels. 1-34 Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 59: Introduction
2Hawk PCI Host Bridge & Multi- Processor Interrupt Controller Introduction Overview This chapter describes the architecture and usage of the PowerPC to PCI Local Bus Bridge (PHB) and the Multi-Processor Interrupt Controller (MPIC) portion of the Hawk ASIC. The Hawk is intended to provide PowerPC 60x (PPC60x) compliant devices access to devices residing on the PCI Local Bus.
Page 60 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller – Read-ahead buffer for reads from the PPC bus. – Four independent software programmable slave map decoders. Interrupt Controller – MPIC compliant. – MPIC programming model. – Support for 16 external interrupt sources and two processors. –...
Page 61: Block Diagram
Block Diagram Block Diagram Figure 2-1. Hawk’s PCI Host Bridge Block Diagram http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 62: Functional Description
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Functional Description Architectural Overview A functional block diagram of the Hawk’s PHB is shown in Figure 2-1. The PHB control logic is subdivided into the following functions: PCI slave, PCI master, PPC slave, and PPC master. The PHB data path logic is subdivided into the following functions: PCI FIFO, PPC FIFO, PCI Input, PPC Input, PCI Output, and PPC Output.
Page 63: Ppc Bus Interface
The PHB will map either PCI memory space or PCI I/O space into PPC address space using four programmable map decoders. These decoders provide windows into the PCI bus from the PPC bus. The most significant http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 64: Figure 2-2. Ppc To Pci Address Decoding
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller 16 bits of the PPC address are compared with the address range of each map decoder, and if the address falls within the specified range, the access is passed on to the PCI. An example of this is shown in Figure 2-2. PPC Bus Address 8 0 8 0 1 2 3 4 Decode is...
Page 65: Ppc Slave
AACK_ and TA_ until after the transaction has completed on the PCI bus. This has the effect of removing all levels of pipelining during compelled PHB accesses. The interdependency between the assertion of http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 66: Table 2-1. Ppc Slave Response Command Types
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller AACK_ and TA_ allows the PPC Slave to assert a retry to the processor in the event that the transaction is unable to complete on the PCI side. It should be noted that any transaction that crosses a PCI word boundary could be disrupted after only having a portion of the data transferred.
Page 67: Ppc Fifo
A 46-bit by 4 entry FIFO is used to hold command information being passed between the PPC Slave and the PCI Master. If write posting has been enabled, then maximum number of transactions that may be posted is http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 68: Ppc Master
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller limited by the abilities of either the data FIFO or the command FIFO. For example, two burst transactions would make the data FIFO the limiting factor for write posting. Four single beat transactions would make the command FIFO be the limiting factor.
Page 69: Table 2-2. Ppc Master Transaction Profiles And Starting Offsets
PCI Slave is continuously stalling during write posted transactions, then further tuning might be needed. This can be accomplished by changing the WXFT (Write Any FIFO Threshold) field within the http://www.motorola.com/computer/literature 2-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 70: Table 2-3. Ppc Master Write Posting Options
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PSATTx registers to recharacterize PHB write posting mechanism. The FIFO threshold should be lowered to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus. The following table summarizes the PHB available write posting options. Table 2-3.
Page 71: Table 2-4. Ppc Master Read Ahead Options
The PPC Master will never perform prefetch reads beyond the address range mapped within the PCI Slave map decoders. As an example, assume PHB has been programmed to respond to PCI address range $10000000 http://www.motorola.com/computer/literature 2-13 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 72: Table 2-5. Ppc Master Transfer Types
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller through $1001FFFF with an offset of $2000. The PPC Master will perform its last read on the PPC60x bus at cache line address $3001FFFC or word address $3001FFF8. The PPC60x bus transfer types generated by the PPC Master depend on the PCI command code and the INV/GBL bits in the PSATTx registers.
Page 73: Ppc Arbiter
EXTL Grant_ XARB3 BiDir Tristate Input CPU0 Request_ Output HAWK Request_ XARB4 Input Input CPU1 Request_ Input HAWK Grant_ XARB5 Input Input EXTL Request_ Input http://www.motorola.com/computer/literature 2-15 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 74 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller While RST_ is asserted, XARB0 through XARB4 will be held in tri-state. If the internal arbiter mode is selected, then XARB0 through XARB3 will be driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST_.
Page 75: Ppc Parity
The time-out length of the bus timer is determined by the XBT field within the GCSR. http://www.motorola.com/computer/literature 2-17 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 76 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PPC Timer is designed to handle the case where an address tenure is not closed out by the assertion of AACK_. The PPC Timer will not handle the case where a data tenure is not closed out by the appropriate number of TA_ assertions.
Page 77: Pci Bus Interface
PPC bus. An example of this is shown in the following figure. http://www.motorola.com/computer/literature 2-19 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 78: Figure 2-4. Pci To Ppc Address Decoding
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI Bus Address 8 0 8 0 1 2 3 4 Decode is >= <= PSADDx Register 7 0 8 0 9 0 0 0 Figure 2-4. PCI to PPC Address Decoding There are no limits imposed by the PHB on how large of an address space a map decoder can represent.
Page 79: Figure 2-5. Pci To Ppc Address Translation
The decoders are prioritized as shown below. Decoder Priority PCI Slave 0 highest PCI Slave 1 PCI Slave 2 PCI Slave 3 lowest http://www.motorola.com/computer/literature 2-21 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 80: Pci Slave
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC Control Registers The MPIC control registers are located within either PCI Memory or PCI I/O space using traditional PCI defined base registers within the predefined 64-byte header. Please see the section on Multi-Processor Interrupt Controller (MPIC) Functional Description for more information.
Page 81: Table 2-7. Pci Slave Response Command Types
During I/O read cycles, the PCI Slave performs integrity checking of the byte enables against the address being presented and assert SERR* in the event there is an error. http://www.motorola.com/computer/literature 2-23 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 82 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave only honors the Linear Incrementing addressing mode. The PCI Slave performs a disconnect with data if any other mode of addressing is attempted. Device Selection The PCI slave will always respond valid decoded cycles as a medium responder.
Page 83 PHB results in the PCI Slave issuing a retry. Parity The PCI Slave supports address parity error detection, data parity generation, and data parity error detection. http://www.motorola.com/computer/literature 2-25 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 84: Pci Fifo
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Cache Support The PCI Slave does not participate in the PCI caching protocol. PCI FIFO A 64-bit by 16 entry FIFO (4 cache lines total) is used to hold data between the PCI Slave and the PPC Master to ensure that optimum data throughput is maintained.
Page 85: Table 2-8. Pci Master Command Codes
0011 I/O Write -- Unsupported -- 0100 Reserved -- Unsupported -- 0101 Reserved PPC Mapped PCI Read 0110 Memory Read Space Write 0111 Memory Write http://www.motorola.com/computer/literature 2-27 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 86 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-8. PCI Master Command Codes (Continued) Entity Addressed TBST* C/BE PCI Command Transfer Type -- Unsupported -- 1000 Reserved -- Unsupported -- 1001 Reserved CONADD/CONDAT Read 1010 Configuration Read CONADD/CONDAT Write 1011 Configuration Write -- Unsupported --...
Page 87 Exclusive Access The PCI Master is not able to initiate exclusive access transactions. Address/Data Stepping The PCI Master does not participate in the Address/Data Stepping protocol. http://www.motorola.com/computer/literature 2-29 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 88: Generating Pci Cycles
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Parity The PCI Master supports address parity generation, data parity generation, and data parity error detection. Cache Support The PCI Master does not participate in the PCI caching protocol. Generating PCI Cycles There are four basic types of bus cycles that can be generated on the PCI bus: Memory and I/O...
Page 89: Figure 2-6. Pci Spread I/O Address Translation
$80000010 is considered a valid transfer. An I/O transfer of four bytes starting at address $80000011 is considered an invalid transfer since it crosses the natural word boundary at address $80000013/$80000014. http://www.motorola.com/computer/literature 2-31 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 90 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Configuration Cycles The PHB uses configuration Mechanism #1 as defined in the PCI Local Bus Specification 2.1 to generate configuration cycles. Please refer to this specification for a complete description of this function. Configuration Mechanism #1 uses an address register/data register format.
Page 91 CONFIG_DATA register causes the PHB to generate a special cycle on the PCI bus. The write data is driven onto AD[31:0] during the special cycle’s data phase. http://www.motorola.com/computer/literature 2-33 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 92: Pci Arbiter
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Generating PCI Interrupt Acknowledge Cycles Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge cycle. Any single byte or combination of bytes may be read from and the actual byte enable pattern used during the read will be passed on to the PCI bus.
Page 93: Table 2-10. Fixed Mode Priority Level Setting
The HEIR setting only covers a small subset of all possible combinations. It is the responsibility of the system designer to connect the request/grant pair in a manner most beneficial to their design goals. http://www.motorola.com/computer/literature 2-35 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 94: Table 2-11. Mixed Mode Priority Level Setting
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller When the arbiter is programmed for round robin priority mode, the arbiter maintains fairness and provides equal opportunity to the requestors by rotating its grants. The contents in “HEIR” field are “don’t cares” when operated in this mode.
Page 95: Table 2-12. Arbitration Setting
PCI bus when in idle state. 3. All other combinations in the PRK setting not specified in the table are invalid and should not be used. http://www.motorola.com/computer/literature 2-37 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 96: Endian Conversion
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller A special function is added to the PCI arbiter to hold the grant asserted through a lock cycle. When the “POL” bit in the PCI arbiter control register is set, the grant associated with the agent initiating the lock cycle will be held asserted until the lock cycle is complete.
Page 97: When Ppc Devices Are Little Endian
PPC60x processors. Note that no data swapping is performed. Address modification happens to the originating address regardless of whether the http://www.motorola.com/computer/literature 2-39 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 98: Phb Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller transaction originates from the PCI bus or the PPC bus. The three low order address bits are exclusive-ORed with a three-bit value that depends on the length of the operand, as shown in the following table. Table 2-13.
Page 99: Error Handling
When any bit in the ESTAT is set, the PHB will attempt to latch as much information as possible about the error in the PPC Error Address (EADDR) and Attribute Registers (EATTR). Information is saved as follows: http://www.motorola.com/computer/literature 2-41 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 100: Watchdog Timers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Error Status Error Address and Attributes XBTO From PPC bus XDPE From PPC bus PRTA From PCI bus PSMA From PCI bus PPER Invalid PSER Invalid Each ESTAT error bit may be programmed to generate a machine check and/or a standard interrupt.
Page 101 The effects on the WDTxCNTL register depend on the byte lanes that are written to during step 2 and are shown in the following table. http://www.motorola.com/computer/literature 2-43 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 102: Pci/Ppc Contention Handling
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-14. WDTxCNTL Programming Byte Lane Selection Results ENAB RELOAD WDTxCNTL Register /RES 8:15 16:23 24:31 Prescaler/ Counter RES/ENAB RELOAD Enable No Change No Change No Change No Change Update from Update from No Change No Change RES/ENAB...
Page 103 The PCI Master must make the determination to perform the resolution function since it must make some decisions on possibly removing a currently pending command from the PPC FIFO. http://www.motorola.com/computer/literature 2-45 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 104 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller There are some performance issues related to bridge lock resolution. PHB offers two mechanism that allow fine tuning of the bridge lock resolution function. Programmable Lock Resolution Consider the scenario where the PPC Slave is hosting a read cycle and the PCI Slave is hosting a posted write transaction.
Page 105: Transaction Ordering
FIFO. All write posted transfers will be completed before a read or compelled write is begun to assure that all transfers are completed in the order issued. http://www.motorola.com/computer/literature 2-47 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 106 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller All PCI Configuration cycles intended for internal PHB registers will also be delayed if PHB is busy so that control bits which may affect write posting do not change until all write posted transactions have completed. For the same reason all PPC60x write posted transfers will also be completed before any access to the PHB PPC registers is begun.
Page 107: Phb Hardware Configuration
Register Base = $FEFF0000 Register Base = $FEFE0000 MPIC Interrupt Type RD[7] Parallel Interrupts Serial Interrupts PPC Arbiter Mode RD[8] Disabled Enabled PCI Arbiter Mode RD[9] Disabled Enabled http://www.motorola.com/computer/literature 2-49 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 108: Multi-Processor Interrupt Controller (Mpic) Functional Description
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-15. PHB Hardware Configuration (Continued) Function Sample Pin(s) Sampled Meaning State PPC:PCI Clock Ratio RD[10:12] Reserved Reserved Reserved Multi-Processor Interrupt Controller (MPIC) Functional Description The MPIC is a multi-processor structured intelligent interrupt controller. MPIC Features: MPIC programming model Supports two processors...
Page 109: Architecture
SI_STA and SI_DAT pins as shown in Figure 2-8. In the parallel mode, 16 external signal pins are used as interrupt inputs (interrupts 0 through 15). http://www.motorola.com/computer/literature 2-51 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 110: Csr's Readability
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCLK SI_STA SI_DAT EXT0 EXT1 EXT2 EXT13EXT14 EXT15 Earliest possible assertion of SI_STA Figure 2-8. Serial Mode Interrupt Scan Using PCLK as a reference, external logic will pulse SI_STA one clock period indicating the beginning of an interrupt scan period. On the same clock period that SI_STA is asserted, external logic will feed the state of EXT0 on the SI_DAT pin.
Page 111: Processor's Current Task Priority
Processor 0 and 1 can generate interrupts which are targeted for the other processor or both processors. There are four Interprocessor Interrupts (IPI) channels. The interrupts are initiated by writing a bit in the IPI dispatch http://www.motorola.com/computer/literature 2-53 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 112: 8259 Compatibility
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller registers. If subsequent IPI’s are initiated before the first is acknowledged, only one IPI will be generated. The IPI channels deliver interrupts in the Direct Mode and can be directed to more than one processor. 8259 Compatibility The MPIC provides a mechanism to support PC-AT compatible chip sets using the 8259 interrupt controller architecture.
Page 113: Timers
2-55 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 114: Block Diagram Description
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller interrupt which is in-service for that processor, and when the priority of that interrupt is the highest of all interrupts pending for that processor, and when that interrupt is not in-service for the other processor. If both destination bits are set for each processor, the interrupt will be delivered to the processor that has a lower task register priority.
Page 115: Figure 2-9. Mpic Block Diagram
Multi-Processor Interrupt Controller (MPIC) Functional Description Int. signals Program Visible Registers Interrupt Interrupt Selector_1 Selector_0 IRR_1 IRR_0 ISR_1 ISR_0 Interrupt Router INT 1 INT 0 Figure 2-9. MPIC Block Diagram http://www.motorola.com/computer/literature 2-57 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 116: Program Visible Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Program Visible Registers These are the registers that software can access. They are described in detail in the MPIC Registers section. Interrupt Pending Register (IPR) The interrupt signals to MPIC are qualified and synchronized to the clock by the IPR.
Page 117: Interrupt Request Register (Irr)
IPR associated with this interrupt. One bit for each processor. http://www.motorola.com/computer/literature 2-59 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 118 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Then one of these bits is delivered to each Interrupt Selector. Since this interrupt source can be multicast, each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor.
Page 119: Programming Notes
8259, the interrupt handler issues an EOI request to the MPIC. This resets the In-Service bit for the 8259 within the MPIC and allows it to recognize higher priority interrupt requests, if any, from http://www.motorola.com/computer/literature 2-61 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 120: Reset State
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller the 8259. If none of the nested interrupt modes of the 8259 are enabled, the interrupt handler issues an EOI request to the 8259. – The device driver interrupt service routine associated with this interrupt vector is invoked.
Page 121: Operation
Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event. If multiple nested interrupts are in service, the EOI command terminates the interrupt service of the http://www.motorola.com/computer/literature 2-63 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 122: Interrupt Acknowledge Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller highest priority source. Once an interrupt is acknowledged, only sources of higher priority will be allowed to interrupt the processor until the EOI command is received. This register should always be written with a value of zero which is the nonspecific EOI command.
Page 123: Effects Of Interrupt Serialization
Hawk’s PCI Host Bridges connected to one PPC60x bus. Please refer to the section http://www.motorola.com/computer/literature 2-65 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 124: Ppc Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller entitled PHB Hardware Configuration for more information. All references to the PPC registers of PHB within this document are made with respect to the base address $FEFF0000. The following conventions are used in the Hawk register charts: R Read Only field.
Page 125: Vendor Id/Device Id Registers
GPREG1(Lower) Vendor ID/Device ID Registers Address $FEFF0000 0 1 2 3 4 5 6 7 8 9 Name VENID DEVID Operation R Reset $1057 $4803 http://www.motorola.com/computer/literature 2-67 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 126: Revision Id Register
VENID (Vendor ID) This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola and is hardwired as a read-only value. This register is duplicated in the PCI Configuration Registers.
Page 127: General Control-Status/Feature Registers
If Bus Hog is not enabled, the PPC master will request the bus in a normal manner. Please refer to the section on PPC Master more information. http://www.motorola.com/computer/literature 2-69 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 128 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller XFBR (PPC Flush Before Read) If set, the PHB will guarantee that all PCI initiated posted write transactions will be completed before any PPC-initiated read transactions will be allowed to complete. When XFBR is clear, there will be no correlation between these transaction types and their order of completion.
Page 129: Ppc Arbiter/Pci Arbiter Control Registers
The encoding of this field is shown in the table below. FBR/FSR/FBW/FSW Effects on Bus Pipelining None None Flatten always Flatten if switching masters http://www.motorola.com/computer/literature 2-71 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 130 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PRI (Priority) If set, the PPC Arbiter will impose a rotating between CPU0 grants. If cleared, a fixed priority will be established between CPU0 and CPU1 grants, with CPU0 having a higher priority than CPU1.
Page 131 PARB5 -> PARB4 -> PARB3 -> PARB2 -> PARB1 -> PARB0 -> HAWK -> PARB6 When using the mixed priority scheme, the encoding of this field is shown in the following table. http://www.motorola.com/computer/literature 2-73 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 132: Hardware Control-Status/Prescaler Adjust Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller HIER Priority ordering, highest to lowest Group 1 -> Group 2 -> Group 3 -> Group 4 Group 4 -> Group 1 -> Group 2 -> Group 3 Group 3 -> Group 4 -> Group 1 -> Group 2 Group 2 ->...
Page 133 If cleared, the PCI Master will only request the PCI bus when a transaction is pending within the PHB FIFOs. http://www.motorola.com/computer/literature 2-75 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 134 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller WLRTx (Write Lock Resolution Threshold) This field is used by the PHB to determine a PPC bound write FIFO threshold at which a bridge lock resolution will create a retry on a pending PCI bound transaction. The encoding of this field is shown in the following table.
Page 135: Ppc Error Test/Error Enable Register
The bits within the ETEST are defined as follows: http://www.motorola.com/computer/literature 2-77 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 136 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller DFLT (Default PPC Master ID) This bit determines which MCHK_ pin will be asserted for error conditions in which the PPC master ID cannot be determined or the PHB was the PPC master. For example, in the event of a PCI parity error for a transaction in which the PHB’s PCI master was not involved, the PPC master ID cannot be determined.
Page 137: Ppc Error Status Register
The Error Status Register (ESTAT) provides an array of status bits pertaining to the various errors that the PHB can detect. The bits within the ESTAT are defined in the following paragraphs. http://www.motorola.com/computer/literature 2-79 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 138 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Address $FEFF0024 0 1 2 3 4 5 6 7 8 9 Name ESTAT Operation Reset OVF (Error Status Overflow) This bit is set when any error is detected and any of the error status bits are already set. It may be cleared by writing a 1 to it;...
Page 139: Ppc Error Address Register
PPER or PSER bits are set in the ESTAT register. Address $FEFF0028 0 1 2 3 4 5 6 7 8 9 Name EAADR Operation Reset $00000000 http://www.motorola.com/computer/literature 2-81 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 140: Ppc Error Attribute Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Error Attribute Register The Error Attribute Register (EATTR) captures attribute information on the various errors that the PHB can detect. If the XDPE, PPER, or PSER bits are set in the ESTAT register, the contents of the EATTR register are zero.
Page 141: Pci Interrupt Acknowledge Register
PCI bus. Upon completion of the PCI interrupt acknowledge cycle, the PHB will present the resulting vector information obtained from the PCI bus as read data. http://www.motorola.com/computer/literature 2-83 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 142: Ppc Slave Address (0,1 And 2) Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Address $FEFF0030 0 1 2 3 4 5 6 7 8 9 Name PIACK Operation Reset $00000000 PPC Slave Address (0,1 and 2) Registers The PPC Slave Address Registers (XSADD0, XSADD1, and XSADD2) contains address information associated with the mapping of PPC memory space to PCI memory/io space.
Page 143: Ppc Slave Offset/Attribute (0, 1 And 2) Registers
WEN (Write Enable) If set, the corresponding PPC Slave is enabled for write transactions. WPEN (Write Post Enable) If set, write posting is enable for the corresponding PPC Slave. http://www.motorola.com/computer/literature 2-85 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 144: Ppc Slave Address (3) Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MEM (PCI Memory Cycle) If set, the corresponding PPC Slave will generate transfers to or from PCI memory space. When clear, the corresponding PPC Slave will generate transfers to or from PCI I/O space using the addressing mode defined by the IOM field.
Page 145: Ppc Slave Offset/Attribute (3) Registers
REN (Read Enable) If set, the corresponding PPC slave is enabled for read transactions. WEN (Write Enable) If set, the corresponding PPC slave is enabled for write transactions. http://www.motorola.com/computer/literature 2-87 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 146: Wdtxcntl Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller WPEN (Write Post Enable) If set, write posting is enabled for the corresponding PPC slave. IOM (PCI I/O Mode) If set, the corresponding PPC slave will generate PCI I/O cycles using spread addressing as defined in the section on Generating PCI Cycles.
Page 147 1011 2048 us 2 min 1100 4096 us 4 min 1101 8192 us 8 min 1110 16,384 us 16 min 1111 32,768 us 32 min http://www.motorola.com/computer/literature 2-89 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 148: Wdtxstat Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller RELOAD (Reload) This field is written with a value that will be used to reload the timer. The RELOAD field may only be modified on the second step of a successful two step arming process. WDTxSTAT Registers Address WDT1STAT - $FEFF0064...
Page 149: Pci Registers
0 9 8 7 6 5 4 3 2 1 0 DEVID VENID STATUS COMMAND CLASS REVID HEADER MIBAR MMBAR $18 - $7C PSADD0 PSOFF0 PSATT0 PSADD1 PSOFF1 PSATT1 http://www.motorola.com/computer/literature 2-91 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 150: Vendor Id/ Device Id Registers
VENID (Vendor ID) This register identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the PPC Registers. DEVID (Device ID) This register identifies the particular device. The Hawk will always return $4803.
Page 151: Pci Command/Status Registers
SERR_ active when a system error is detected. The Status Register (STATUS) is used to record information for PCI bus related events. The bits within the STATUS register are defined as follows: http://www.motorola.com/computer/literature 2-93 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 152 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller P66M (PCI66 MHz) This bit indicates the PHB is capable of supporting a 66.67 MHz PCI bus. FAST (Fast Back-to-Back Capable) This bit indicates that the PHB is capable of accepting fast back-to-back transactions with different targets.
Page 153: Revision Id/Class Code Registers
Header Type Register Offset Name HEADER Operation Reset The Header Type Register (Header) identifies the PHB as the following: Header Type Single Function Configuration Header http://www.motorola.com/computer/literature 2-95 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 154: Mpic I/O Base Address Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller MPIC I/O Base Address Register Offset 0 9 8 7 6 5 4 3 2 1 0 Name MIBAR BASE Operation R/W Reset $0000 $0000 The MPIC I/O Base Address Register (MIBAR) controls the mapping of the MPIC control registers in PCI I/O space.
Page 155: Mpic Memory Base Register
BASE (Base Address) These bits define the memory space base address of the MPIC control registers. The MBASE decoder is disabled when the BASE value is zero. http://www.motorola.com/computer/literature 2-97 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 156: Pci Slave Address (0,1,2 And 3) Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PCI Slave Address (0,1,2 and 3) Registers Offset PSADD0 - $80 PSADD1 - $88 PSADD2 - $90 PSADD3 - $98 0 9 8 7 6 5 4 3 2 1 0 Name PSADDx START Operation...
Page 157: Pci Slave Attribute/Offset (0,1,2 And 3) Registers
WEN (Write Enable) If set, the corresponding PCI slave is enabled for write transactions. REN (Read Enable) If set, the corresponding PCI slave is enabled for read transactions. http://www.motorola.com/computer/literature 2-99 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 158: Config_Address Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller RMFTx (Read Multiple FIFO Threshold) This field is used by the PHB to determine a FIFO threshold at which to continue prefetching data from local memory during PCI read multiple transactions. This threshold applies to subsequent prefetch reads since all initial prefetch reads will be four cache lines.
Page 159 Perspective from the PPC bus in Little-Endian mode: Offset $CFC $CFD $CFE $CFF Bit (DL) 0 1 2 3 4 5 6 7 8 9 Name CONFIG_ADDRESS Operation Reset http://www.motorola.com/computer/literature 2-101 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 160 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The register fields are defined as follows: REG (Register Number) Configuration Cycles: Identifies a target double word within a target’s configuration space. This field is copied to the PCI AD bus during the address phase of a Configuration cycle. Special Cycles: This field must be written with all zeros.
Page 161: Config_Data Register
$CFF Bit (DL) 0 1 2 3 4 5 6 7 8 9 Name CONFIG_DATA Data ‘A’ Data ‘B’ Data ‘C’ Data ‘D’ Operation Reset http://www.motorola.com/computer/literature 2-103 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 162: Mpic Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Perspective from the PPC bus in Little-Endian mode: Offset $CF8 $CF9 $CFA $CFB Bit (DH) 0 1 2 3 4 5 6 7 8 9 Name CONFIG_DATA Data ‘D’ Data ‘C’ Data ‘B’ Data ‘A’...
Page 163: Feature Reporting Register 0
TIMER 2 VECTOR-PRIORITY REGISTER $011a0 TIMER 2 DESTINATION REGISTER $011b0 TIMER 3 CURRENT COUNT REGISTER $011c0 TIMER 3 BASE COUNT REGISTER $011d0 TIMER 3 VECTOR-PRIORITY REGISTER $011e0 http://www.motorola.com/computer/literature 2-105 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 164 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Table 2-19. MPIC Register Map (Continued) 0 9 8 7 6 5 4 3 2 1 0 TIMER 3 DESTINATION REGISTER $011f0 INT. SRC. 0 VECTOR-PRIORITY REGISTER $10000 INT. SRC. 0 DESTINATION REGISTER $10010 INT.
Page 165 IPI 2 DISPATCH REGISTER PROC. 1 $21060 IPI 3 DISPATCH REGISTER PROC. 1 $21070 CURRENT TASK PRIORITY REGISTER PROC. 1 $21080 IACK REGISTER $210a0 EOI REGISTER $210b0 http://www.motorola.com/computer/literature 2-107 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 166 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Feature Reporting Register Offset $01000 0 9 8 7 6 5 4 3 2 1 0 Name FEATURE REPORTING NIRQ NCPU Operation Reset $00F NIRQ (Number of IRQs) The number of the highest external IRQ source supported.
Page 167: Table 2-20. Cascade Mode Encoding
Processor 0 (Mode used on Version $02 of MPIC). Table 2-21. Tie Mode Encoding Mode Processor 0 always selected Swap between Processor’s http://www.motorola.com/computer/literature 2-109 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 168: Vendor Identification Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Vendor Identification Register Offset $01080 0 9 8 7 6 5 4 3 2 1 0 Name VENDOR IDENTIFICATION Operation Reset There are two fields in the Vendor Identification Register which are not defined for the MPIC implementation but are defined in the MPIC specification.
Page 169: Ipi Vector/Priority Registers
0 will not enable interrupts. VECTOR This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-111 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 170: Spurious Vector Register
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Spurious Vector Register Offset $010E0 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation R Reset VECTOR This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch. Timer Frequency Register Offset $010F0...
Page 171: Timer Current Count Registers
Count Inhibit bit is the Base Count Register is zero. When the timer counts down to zero, the Current Count register is reloaded from the Base Count register and the timer’s interrupt becomes pending in MPIC processing. http://www.motorola.com/computer/literature 2-113 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 172: Timer Basecount Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timer Basecount Registers Offset Timer 0 - $01110 Timer 1 - $01150 Timer 2 - $01190 Timer 3 - $011D0 0 9 8 7 6 5 4 3 2 1 0 Name TIMER BASECOUNT Operation Reset...
Page 173: Timer Vector/Priority Registers
0 will not enable interrupts. VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-115 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 174: Timer Destination Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Timer Destination Registers Offset Timer 0 - $01130 Timer 1 - $01170 Timer 2 - $011B0 Timer 3 - $011F0 0 9 8 7 6 5 4 3 2 1 0 Name TIMER DESTINATION Operation Reset...
Page 175 Note that a priority level of 0 will not enable interrupts. VECTOR (Vector) This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector. http://www.motorola.com/computer/literature 2-117 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 176: External Source Destination Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller External Source Destination Registers Offset Int Src 0 - $10010 Int Src 2 -> Int Src 15 - $10030 -> $101F0 0 9 8 7 6 5 4 3 2 1 0 Name EXTERNAL SOURCE DESTINATION Operation...
Page 177: Phb-Detected Errors Destination Register
These interrupts operate in the Distributed interrupt delivery mode. P1 (Processor 1) The interrupt is pointed to processor 1. P0 (Processor 0) The interrupt is pointed to processor 0. http://www.motorola.com/computer/literature 2-119 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 178: Interprocessor Interrupt Dispatch Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Interprocessor Interrupt Dispatch Registers Offset Processor 0 $20040, $20050, $20060, $20070 Processor 1 $21040, $21050, $21060, $21070 0 9 8 7 6 5 4 3 2 1 0 Name IPI DISPATCH Operation Reset There are four Interprocessor Interrupt Dispatch Registers.
Page 179: Interrupt Acknowledge Registers
The associated bit in the Interrupt Pending Register is cleared. Reading this register will update the In-Service register. VECTOR (Vector) This vector is returned when the Interrupt Acknowledge register is read. http://www.motorola.com/computer/literature 2-121 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 180: End-Of-Interrupt Registers
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller End-of-Interrupt Registers Offset Processor 0 $200B0 Processor 1 $210B0 0 9 8 7 6 5 4 3 2 1 0 Name Operation Reset EOI (End of Interrupt) There is one EOI register per processor. EOI Code values other than 0 are currently undefined.
Page 181: Introduction
3System Memory Controller (SMC) Introduction The SMC in the Hawk ASIC is equivalent to the former Falcon Pair portion of a Falcon/Raven chipset. As were its predecessors, it is designed for the MVME family of boards. The SMC has interfaces between the PowerPC60x bus (also called PPC60x bus or PPC bus) and SDRAM, ROM/Flash, and its Control and Status Register sets (CSR).
Page 182: Block Diagrams
System Memory Controller (SMC) Error Notification for SDRAM – Software programmable Interrupt on Single/Double-Bit Error. – Error address and Syndrome Log Registers for Error Logging. – Does not provide TEA_ on Double-Bit Error. (Chip has no TEA_ pin.) ROM/Flash Interface –...
Page 183: Figure 3-1. Hawk Used With Synchronous Dram In A System
Address & Control PowerPC Address &Control PowerPC Check SDRAM Address Parity (4 bits) Check Bits (8 Bits) Figure 3-1. Hawk Used with Synchronous DRAM in a System http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 184: Figure 3-2. Hawk's System Memory Controller Internal Data Paths
System Memory Controller (SMC) PowerPC SDRAM Side Side (8 Bits) Latched D (64 Bits) (64 Bits) (8 Bits) (8 Bits) (8 Bits) Uncorrected Data (64 Bits) Figure 3-2. Hawk’s System Memory Controller Internal Data Paths Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ...
Page 185: Figure 3-3. Overall Sdram Connections (4 Blocks Using Register Buffers)
BA,RA,RAS_, CAS_,WE_,DQM RD0-63 CKD0-7 SDRAM SDRAM SDRAM SDRAM BLOCK A BLOCK B BLOCK C BLOCK D Figure 3-3. Overall SDRAM Connections (4 Blocks using Register Buffers) http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 186: Functional Description
System Memory Controller (SMC) SDRAM PPC60x Ctrl MEM Ctrl PPC60x & SLAVE ROM/Flash INTERFACE CONTROL REFRESHER MEM Addr PPC60x Attr PPC60x SDRAM /SCRUBBER ADDRESS ADDRESS ARBITER DECODER MULTIPLEXOR PPC60x Addr STATUS SDRAM /CONTROL ERROR I2C Bus JTAG REGISTERS LOGGER INTERFACE MEM Data PPC60x Data DATA...
Page 187: Single-Beat Reads/Writes
SDRAM Speed Attributes Register, which is described in the Register portion of this section. Refer to the table below for some specific timing numbers. http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 188: Table 3-1. 60X Bus To Sdram Estimated Access Timing At 100Mhz With Pc100 Sdrams (Cas_Latency Of 2)
System Memory Controller (SMC) Table 3-1. 60x Bus to SDRAM Estimated Access Timing at 100MHz with PC100 SDRAMs (CAS_latency of 2) Access Type Access Time Comments (tB1-tB2-tB3-tB4) 4-Beat Read after idle, 10-1-1-1 SDRAM Bank Inactive 4-Beat Read after idle, 12-1-1-1 SDRAM Bank Active - Page Miss 4-Beat Read after idle, 7-1-1-1...
Page 189: Sdram Organization
The 72-bit, unbuffered DIMMs can be used as long as AC timing is met and they use the components listed. All components must be organized with 4 internal banks. http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 190: Rom/Flash Speeds
System Memory Controller (SMC) ROM/Flash Speeds The SMC provides the interface for two blocks of ROM/Flash. Access times to ROM/Flash are programmable for each block. Access times are also affected by block width. Refer to the following tables for some specific timing numbers.
Page 191 Bits Bits Bits Bits Bits Bits Bits Bits Bits 4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes) 1-Beat Write http://www.motorola.com/computer/literature 3-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 192: Responding To Address Transfers
System Memory Controller (SMC) Note The information in Table 3-4 applies to access timing when configured for devices with an access time equal to 5 clock periods. Table 3-5. PPC60 x Bus to ROM/Flash Access Timing (30ns @ 100 MHz) CLOCK PERIODS REQUIRED FOR: Total Clocks...
Page 193: Completing Data Transfers
PPC60 x Address Parity The Hawk has 4 AP pins for generating and checking PPC60x address bus parity. http://www.motorola.com/computer/literature 3-13 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 194: Cache Coherency
System Memory Controller (SMC) During any address transfer cycle on the PPC60x, the SMC checks each of the 4 8-bit PPC60x address lanes and its corresponding AP signal for odd parity. If any of the 4 lanes has even parity, the SMC logs the error in the CSR and can generate a machine check if so enabled.
Page 195: Ecc
The SMC checks data from the SDRAM during single- and four-beat reads, during single-beat writes, and during scrubs. Table 3-6 shows the actions it takes for different errors during these accesses. http://www.motorola.com/computer/literature 3-15 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 196: Table 3-6. Error Reporting
System Memory Controller (SMC) Note that the SMC does not assert TEA_ on double-bit errors. In fact, the SMC does not have a TEA_ signal pin and it assumes that the system does not implement TEA_. The SMC can, however, assert machine check (MCHK0_) on double-bit error.
Page 197: Error Logging
$FFFFFFFF. The overall enable and write enable bits are always cleared at reset. The reset vector enable bit is cleared or set at reset depending on external jumper configuration. This allows the board http://www.motorola.com/computer/literature 3-17 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 198 System Memory Controller (SMC) designer to use external jumpers to enable/disable Block A/B ROM/Flash as the source of reset vectors. 2. The base address for each block is software programmable. At reset, Block A’s base address is $FF000000 and Block B’s base address is $FF400000.
Page 199 Upper $XX00000C $000004 Lower $XX00000D $000005 Lower $XX00000E $000006 Lower $XX00000F $000007 Lower $XXFFFFF8 $7FFFFC Upper $XXFFFFF9 $7FFFFD Upper $XXFFFFFA $7FFFFE Upper $XXFFFFFB $7FFFFF Upper http://www.motorola.com/computer/literature 3-19 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 200 System Memory Controller (SMC) Table 3-7. PPC60 x to ROM/Flash (16 Bit Width) Address Mapping (Continued) PPC60x A0-A31 ROM/Flash A22-A0 ROM/Flash Device Selected $XXFFFFFC $7FFFFC Lower $XXFFFFFD $7FFFFD Lower $XXFFFFFE $7FFFFE Lower $XXFFFFFF $7FFFFF Lower Table 3-8. PPC60 x to ROM/Flash (64 Bit Width) Address Mapping PPC60x A0-A31 ROM/Flash A22-A0 ROM/Flash Device Selected...
Page 201: I2C Interface
EEPROM devices are all slaves. The I C bus supports 7-bit addressing mode and transmits data one byte at a time in a serial fashion http://www.motorola.com/computer/literature 3-21 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 202: I2C Byte Write
System Memory Controller (SMC) with the most significant bit (MSB) being sent out first. Five registers are required to perform the I C bus data transfer operations. These are the I Clock Prescaler Register, I C Control Register, I C Status Register, I Transmitter Data Register, and I C Receiver Data Register.
Page 203 The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master’s possession of the I C bus. http://www.motorola.com/computer/literature 3-23 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 204: Figure 3-5. Programming Sequence For I2C Byte Write
System Memory Controller (SMC) DEVICE ADDR WORD ADDR DATA START STOP ACK from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG CMPLT=ACKIN=1? LOAD “WORD ADDR”...
Page 205: I2C Random Read
The stop sequence will relinquish the ASIC master’s possession of the I C bus. http://www.motorola.com/computer/literature 3-25 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 206: Figure 3-6. Programming Sequence For I2C Random Read
System Memory Controller (SMC) DEVICE ADDR WORD ADDR x DEVICE ADDR START START DATA x STOP ACK and DATA from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG READ I2C STATUS REG...
Page 207: I2C Current Address Read
The stop sequence will relinquish the ASIC master’s possession of the I C bus. http://www.motorola.com/computer/literature 3-27 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 208: Figure 3-7. Programming Sequence For I2C Current Address Read
System Memory Controller (SMC) DEVICE ADDR DATA of (last ADDR+1) START STOP ACK and DATA from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+RD BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG CMPLT=ACKIN=1? LOAD “DUMMY DATA”...
Page 209: I2C Page Write
The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master’s possession of the I C bus. http://www.motorola.com/computer/literature 3-29 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 210: Figure 3-8. Programming Sequence For I2C Page Write
System Memory Controller (SMC) DEVICE ADDR WORD ADDR 1 DATA 1 DATA n START STOP ACK from Slave Device BEGIN READ I2C STATUS REG CMPLT=1? LOAD “$09” (START CONDITION) TO I2C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO I2C TRANSMITTER DATA REG READ I2C STATUS REG CMPLT=ACKIN=1? LOAD “DATA1 ...
Page 211: I2C Sequential Read
The I C sequential read operation is terminated when the I C master controller does not respond with an acknowledge. This can be http://www.motorola.com/computer/literature 3-31 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 212 System Memory Controller (SMC) accomplished by setting only the i2_enbl bit in the I C Control Register before receiving the last data word. A stop sequence then must be transmitted to the slave device by first setting the i2_stop and i2_enbl bits in the I C Control Register and then writing a dummy data (data=don’t care) to the I...
Page 213: Figure 3-9. Programming Sequence For I2C Sequential Read
Stop condition should be generated to abort the transfer after a software wait loop (~1ms) has been expired Figure 3-9. Programming Sequence for I2C Sequential Read http://www.motorola.com/computer/literature 3-33 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 214: Refresh/Scrub
System Memory Controller (SMC) Refresh/Scrub The SMC performs refresh by doing a burst of 4 CAS-Before-RAS (CBR) refresh cycles to each block of SDRAM once every 60us. It performs scrubs by replacing every 128th refresh burst with a read cycle to 8 bytes in each block of SDRAM.
Page 215: Programming Model
CSR write accesses are restricted to a size of 1 or 4 bytes and they must be aligned. Register Summary Table 3-9 shows a summary of the internal and external register set. http://www.motorola.com/computer/literature 3-35 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 216: Table 3-9. Register Summary
System Memory Controller (SMC) Table 3-9. Register Summary BIT # ----> FEF80000 VENDID DEVID FEF80008 REVID STAT FEF80010 RAM A RAM B RAM C RAM D FEF80018 RAM A BASE RAM B BASE RAM C BASE RAM D BASE FEF80020 CLK FREQUENCY FEF80028 FEF80030...
Page 217 DPE_DP GWDP FEF80070 DPE_A FEF80078 DPE_DH FEF80080 DPE_DL FEF80090 I2_PRESCALE_VAL FEF80098 FEF800A0 FEF800A8 I2_DATAWR FEF800B0 I2_DATARD FEF800C0 RAM E RAM F RAM G RAM H http://www.motorola.com/computer/literature 3-37 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 218: Detailed Register Bit Descriptions
System Memory Controller (SMC) Table 3-9. Register Summary (Continued) FEF800C8 RAM E BASE RAM F BASE RAM G BASE RAM H BASE FEF800D0 FEF800E0 APE_TT APE_AP FEF800E8 APE_A FEF80100 CTR32 FEF88300 FEF88000 FEF8FFF8 EXTERNAL REGISTER SET BIT # ----> Notes 1. All empty bit fields are reserved and read as zeros. 2.
Page 219: Vendor/Device Register
READ ONLY Reset $1057 $4803 VENDID This read-only register contains the value $1057. It is the vendor number assigned to Motorola Inc. DEVID This read-only register contains the value $4803. It is the device number for the Hawk. http://www.motorola.com/computer/literature 3-39...
Page 220: Revision Id/ General Control Register
System Memory Controller (SMC) Revision ID/ General Control Register Address $FEF80008 Name REVID Operation READ ONLY Reset tben en (tben_en) controls the enable for the p1_tben and p0_tben output signals. When tben_en is set, the I Clm_ input pin becomes the p1_tben output pin and the ercs_output pin becomes the p0_tben output pin.
Page 221: Sdram Enable And Size Register (Blocks A, B, C, D)
SDRAM refresh to occur by waiting for the 32-bit counter (see Detailed Register Bit Descriptions further on in this chapter) to increment at least 100 times. The wait period needs to happen during the envelope. http://www.motorola.com/computer/literature 3-41 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 222: Table 3-10. Block_A/B/C/D/E/F/G/H Configurations
System Memory Controller (SMC) ram a/b/c/d en ram a/b/c/d en enables 60x accesses to the corresponding block of SDRAM when set, and disables them when cleared. Note that ram e/f/g/h en are located at $FEF800C0 (refer to the section on SDRAM Enable and Size Register (Blocks E,F,G,H) further on in this chapter for more information.) They operate the same for...
Page 223: Sdram Base Address Register (Blocks A/B/C/D)
RAM A/B/C/D BASE These control bits define the base address for their block’s SDRAM. RAM A/B/C/D BASE bits 0-7/8-15/16-23/24- 31 correspond to PPC60x address bits 0 - 7. For larger SDRAM sizes, http://www.motorola.com/computer/literature 3-43 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 224: Clk Frequency Register
System Memory Controller (SMC) the lower significant bits of A/B/C/D BASE are ignored. This means that the block’s base address will always appear at an even multiple of its size. Remember that bit 0 is MSB. Note RAM_E/F/G/H_BASE are located at $FEF800C8 (refer to the section on SDRAM Base Address Register (Blocks E/F/G/H).
Page 225: Ecc Control Register
This prevents the generation of illegal cycles to the SDRAM when refdis is updated. http://www.motorola.com/computer/literature 3-45 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 226: Figure 3-10. Read/Write Check-Bit Data Paths
System Memory Controller (SMC) rwcb When set, rwcb causes reads and writes to SDRAM from the PPC60x bus to access check-bit data rather than normal data. The data path used for reading and writing check bits is D0-D7. Each 8-bit check-bit location services 64 bits of normal data.
Page 227 When the int bit is set, the Hawk’s internal SMC_INT signal to the MPIC is asserted. http://www.motorola.com/computer/literature 3-47 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 228 System Memory Controller (SMC) dpien When dpien is set, the logging of a PPC60x data parity error causes the int bit to be set if it is not already. When the int bit is set, the Hawk’s internal SMC_INT signal to the MPIC is asserted. sien When sien is set, the logging of a single-bit error causes the int bit to be set if it is not already.
Page 229: Error Logger Register
When the SMC logs a single-bit error, the syndrome code indicates which bit was in error. (Refer to the section on Codes.) http://www.motorola.com/computer/literature 3-49 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 230: Error_Address Register
System Memory Controller (SMC) ERR_SYNDROME ERR_SYNDROME reflects the syndrome value at the last logging of an error. This eight-bit code indicates the position of the data error. When all the bits are zero, there was no error. Note that if the logged error was multiple-bit then these bits are meaningless.
Page 231: Scrub/Refresh Register
Since SCRUB_FREQUENCY is cleared to 0’s at power-up reset, scrubbing is disabled until software programs a non-zero value into it. http://www.motorola.com/computer/literature 3-51 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 232: Scrub Address Register
System Memory Controller (SMC) Scrub Address Register Address $FEF80048 Name SCRUB ADDRESS Operation READ/WRITE Reset SCRUB ADDRESS These bits form the address counter used by the scrubber for all blocks of SDRAM. The scrub address counter increments by one each time a scrub to one location completes to all of the blocks of SDRAM.
Page 233: Rom A Base/Size Register
Block A. When rom_a_64 is cleared, Block A is 16 bits wide, where each half of SMC interfaces to 8 bits. When rom_a_64 is set, http://www.motorola.com/computer/literature 3-53 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 234: Table 3-11. Rom Block A Size Encoding
System Memory Controller (SMC) Block A is 64 bits wide, where each half of the SMC interfaces to 32 bits. rom_a_64 matches the value that was on the RD2 pin at power- up reset. It cannot be changed by software. rom a siz The rom a siz control bits are the size of ROM/Flash for Block A.
Page 235: Table 3-13. Read/Write To Rom/Flash
Aligned Normal termination, but no write to ROM/Flash write 4-byte Aligned Normal termination, write occurs to ROM/Flash write 2,3,5,6,7, No Response 8,32-byte read Normal Termination http://www.motorola.com/computer/literature 3-55 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 236: Rom B Base/Size Register
System Memory Controller (SMC) ROM B Base/Size Register Address $FEF80058 Name ROM B BASE Operation READ/WRITE READ ZERO Reset $FF4 PL Writes to this register must be enveloped by a period of time in which no accesses to ROM/Flash Block B, occur. A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC’s registers before and after the write.
Page 237 When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is cleared they are disabled. Refer back to Table 3-13 for more details. http://www.motorola.com/computer/literature 3-57 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 238: Rom Speed Attributes Registers
System Memory Controller (SMC) ROM Speed Attributes Registers Address $FEF80060 Name Operation READ ZERO READ ZERO READ ZERO Reset rom_a_spd0,1 rom_a_spd0,1 determine the access timing used for ROM/Flash Block A. The encoding of these bits are shown in Table 3-15. The device access times shown in the table are conservative and allow time for buffers on address, control, and data signals.
Page 239: Data Parity Error Log Register
Note Note that the Hawk does not check parity during cycles in which there is a qualified ARTRY_ at the same time as the TA_ http://www.motorola.com/computer/literature 3-59 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 240: Data Parity Error Address Register
System Memory Controller (SMC) dpe_me When dpe_me is set, the transition of the dpelog bit from false to true causes the Hawk to pulse its machine check interrupt request pin (MCHK0_) true. When dpe_me is cleared, the Hawk does not assert its MCHK0_ pin based on the dpelog bit. GWDP The GWDP0-GWDP7 bits are used to invert the value that is driven onto DP0-DP7 respectively during reads to the Hawk.
Page 241: Data Parity Error Lower Data Register
After power-up, I2_PRESCALE_VAL is initialized to $1F3 which produces a 100KHz I C gated clock signal based on a 100.0MHz system clock. Writes to this register will be restricted to 4-bytes only. http://www.motorola.com/computer/literature 3-61 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 242: I2C Control Register
System Memory Controller (SMC) I2C Control Register Address $FEF80098 Name Operation READ ZERO READ ZERO READ ZERO Reset i2_start When set, the I C master controller generates a start sequence on the I C bus on the next write to the I C Transmitter Data Register and clears the i2_cmplt bit in the I C Status Register.
Page 243: I2C Status Register
C master controller has successfully completed the requested I C operation and cleared at the beginning of every valid I C operation. This bit is also set after power-up. http://www.motorola.com/computer/literature 3-63 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 244: I2C Transmitter Data Register
System Memory Controller (SMC) I2C Transmitter Data Register Address $FEF800A8 Name I2_DATAWR Operation READ ZERO READ ZERO READ ZERO READ/WRITE Reset 0 PL I2_DATAWR The I2_DATAWR contains the transmit byte for I data transfers. If a value is written to I2_DATAWR when the i2_start and i2_enbl bits in the I C Control Register are set, a start sequence is generated immediately followed by the transmission of the contents of...
Page 245: I2C Receiver Data Register
A simple way to do this is to perform at least two read accesses to this or another register before and after the write. http://www.motorola.com/computer/literature 3-65 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 246: Sdram Base Address Register (Blocks E/F/G/H)
System Memory Controller (SMC) Additionally, sometime during the envelope, before or after the write, all of the SDRAMs open pages must be closed and the Hawk’s open page tracker reset. The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32-Bit Counter to increment...
Page 247 SDRAM responds at the same address as the CSR, ROM/Flash, External Register Set, or any other slave on the PowerPC bus. http://www.motorola.com/computer/literature 3-67 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 248: Sdram Speed Attributes Register
System Memory Controller (SMC) SDRAM Speed Attributes Register Address $FEF800D0 Name Operation Reset The SDRAM Speed Attributes Register should be programmed based on the SDRAM device characteristics and the Hawk’s operating frequency to ensure reliable operation. In order for writes to this register to work properly they should be separated from any SDRAM accesses by a refresh before the write and by another refresh after the write.
Page 249: Table 3-16. Trc Encoding
SMC assumes the SDRAM requires to satisfy its tRAS parameter. These bits are encoded as follows: Table 3-17. tras Encoding tras0,1 Minimum Clocks for tras http://www.motorola.com/computer/literature 3-69 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 250: Address Parity Error Log Register
System Memory Controller (SMC) swr_dpl swr_dpl causes the SMC to always wait until four clocks after the write command portion of a single write before allowing a precharge to occur. This function may not be required. If such is the case, swr_dpl can be cleared by software.
Page 251: Address Parity Error Address Register
CTR32 CTR32 is a 32-bit, free-running counter that increments once per microsecond if the CLK_FREQUENCY register has been programmed properly. Notice that CTR32 is cleared by power-up and local reset. http://www.motorola.com/computer/literature 3-71 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 252: External Register Set
System Memory Controller (SMC) Note When the system clock is a fractional frequency, such as 66.67MHz, CTR32 will count at a fractional amount faster or slower than 1MHz, depending on the programming of the CLK_FREQUENCY Register. External Register Set Address $FEF88000 - $FEF8FFF8 Name EXTERNAL REGISTER SET...
Page 253: Tben Register
0, the P1_TBEN pin is low and when p1_tben is 1, the P1_TBEN pin is high. When the tben_en bit is cleared, p1_tben has no effect on any pin. http://www.motorola.com/computer/literature 3-73 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 254: Software Considerations
System Memory Controller (SMC) p0_tben When the tben_en bit is set, the ERCS_ output pin becomes the P1_TBEN output pin and it tracks the value on p0_tben. When p0_tben is 0, the P0_TBEN pin is low and when p1_tben is 1, the P0_TBEN pin is high.
Page 255: Initializing Sdram Related Control Registers
SDRAM for at least one refresh period before and after it programs the SDRAM speed attribute bits. http://www.motorola.com/computer/literature 3-75 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 256: Sdram Size
System Memory Controller (SMC) SDRAM Size The SDRAM size control bits come up from power-up reset cleared to zero. Once software has determined the correct size for an SDRAM block, it should set the block’s size bits to match. The value programmed into the size bits tells the Hawk how big the block is (for map decoding) and how to translate that block’s 60x addresses to SDRAM addresses.
Page 257: Sdram Control Registers Initialization Example
CAS latency of 3 is all that is supported for this block. c. If a CAS latency of 2 is supported, check SPD byte 23 to determine the CAS_latency _2 cycle time. If the CAS_latency_2 http://www.motorola.com/computer/literature 3-77 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 258: Table 3-18. Deriving Tras, Trp, Trcd And Trc Control Bit Values From Spd Information
System Memory Controller (SMC) cycle time is less than or equal to the period of the system clock then this block can operate with a CAS latency of 2. Otherwise a CAS latency of 3 is all that is supported for this block. If any block does not support a CAS latency of 2, then cl3 is to be set.
Page 259 6. tRCD_CLK is tRCD expressed in CLK periods. 7. Use tRC from the SDRAM block that has the slowest tRC. 8. tRC_CLK is tRC expressed in CLK periods. http://www.motorola.com/computer/literature 3-79 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 260 System Memory Controller (SMC) 9. Determine the size for each block that is present. (Do not actually program the Hawk’s size bits at this point. You use this information to program them later.) Each block’s size can be determined using the following algorithm: a.
Page 261: Table 3-19. Programming Sdram Siz Bits
11. Wait for at least one SDRAM refresh to complete. A simple way to do this is to wait for the 32-bit counter to increment at least 100 times. Refer to the section titled 32-Bit Counter for more http://www.motorola.com/computer/literature 3-81 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 262: Optional Method For Sizing Sdram
System Memory Controller (SMC) information. Note that the refdis control bit must not be set in the ECC Control Register. 12. Now that at least one refresh has occurred since SDRAM was last accessed, it is okay to write to the SDRAM control registers. a.
Page 263 Make sure that no other devices are set up to respond in the range $00000000 - $20000000. 2. For each of the Blocks A through H: http://www.motorola.com/computer/literature 3-83 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 264 System Memory Controller (SMC) a. Set the block’s base address to $00000000. Refer to the sections titled SDRAM Base Address Register (Blocks A/B/C/D) SDRAM Enable and Size Register (Blocks E,F,G,H). b. Enable the block and make sure that the other seven blocks are disabled.
Page 265: Table 3-20. Address Lists For Different Block Size Checks
3. This needed only to check for non-zero size. 3. Wait enough time to allow at least 1 SDRAM refresh to occur before beginning any SDRAM accesses. http://www.motorola.com/computer/literature 3-85 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 266: Ecc Codes
System Memory Controller (SMC) ECC Codes When the Hawk reports a single-bit error, software can use the syndrome that was logged by the Hawk to determine which bit was in error. Table 3-21 shows the syndrome for each possible single bit error. Table 3-22 shows the same information ordered by syndrome.
Page 267: Table 3-22. Single Bit Errors Ordered By Syndrome Code
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Page 268 System Memory Controller (SMC) Table 3-22. Single Bit Errors Ordered by Syndrome Code (Continued) rd28 rd36 3-88 Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 269: General Information
64-bit VMEbus to PCI interface in one device. Designed by Tundra Semiconductor Corporation in consultation with Motorola, the Universe II is compliant with the VME64 specification and is tuned to the new generation of high speed processors. The Universe II is ideally suited for CPU boards acting as both master and slave in the VMEbus system and is particularly fitted for PCI local systems.
Page 270: Functional Description
Universe II (VMEbus to PCI) Chip – BLT, ADOH, RMW, LOCK Automatic initialization for slave-only applications Flexible register set, programmable from both the PCI bus and VMEbus ports Full VMEbus system controller functionality IEEE 1149.1 JTAG testability support, and Available in 313-pin Plastic BGA and 324-pin contact Ceramic Functional Description Architectural Overview This section introduces the general architecture of the Universe II.
Page 271: Interrupter And Interrupt Handler
FIFO VMEbus Slave Master coupled read logic Interrupt Channel Interrupt Handler Interrupts Interrupts Interrupter Register Channel 1894 9609 Figure 4-1. Architectural Diagram for the Universe II http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 272 Universe II (VMEbus to PCI) Chip VMEbus Interface Universe II as VMEbus Slave The Universe II VME Slave Channel accepts all of the addressing and data transfer modes documented in the VME64 specification (except A64 and those intended to support 3U applications, that is, A40 and MD32). Incoming write transactions from the VMEbus may be treated as either coupled or posted, depending upon the programming of the VMEbus slave image.
Page 273 (Refer to the sections entitled Exclusive Accesses and RMW and ADOH Cycles in the Universe II User Manual, Appendix B, Related Documentation, for a full description of this functionality.) http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 274 Universe II (VMEbus to PCI) Chip Universe II as PCI Master The Universe II becomes PCI master when the PCI Master Interface is internally requested by the VME Slave Channel or the DMA Channel. There are mechanisms provided which allow the user to configure the relative priority of the VME Slave Channel and the DMA Channel.
Page 275: Dma Controller
Linked-list operation is initiated through a pointer in an internal Universe II register, but the linked list itself resides in PCI bus memory. http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 276: Registers - Universe Ii Control And Status Registers (Ucsr)
Universe II (VMEbus to PCI) Chip Registers - Universe II Control and Status Registers (UCSR) The Universe II Control and Status Registers (UCSR) facilitate host system configuration and allow the user to control Universe II operational characteristics. The UCSRs are divided into three groups: PCI Configuration Space (PCICS) VMEbus Control and Status Registers (VCSR), and Universe II Device Specific Status Registers (UDSR)
Page 277: Universe Ii Register Map
PCI Reserved PCI Configuration Miscellaneous 1 Register PCI_MISC1 040 - 0FF PCI Unimplemented PCI Slave Image 0 Control LSI0_CTL PCI Slave Image 0 Base Address Register LSI0_BS http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 278 Universe II (VMEbus to PCI) Chip Table 4-1. Universe II Register Map (Continued) Offset Register Name PCI Slave Image 0 Bound Address Register LSI0_BD PCI Slave Image 0 Translation Offset LSI0_TO Universe II Reserved PCI Slave Image 1 Control LSI1_CTL PCI Slave Image 1 Base Address Register LSI1_BS PCI Slave Image 1 Bound Address Register...
Page 279 V3_STATID VIRQ4 STATUS/ID V4_STATID VIRQ5 STATUS/ID V5_STATID VIRQ6 STATUS/ID V6_STATID VIRQ7 STATUS/ID V7_STATID 340 - 3FC Universe II Reserved Master Control MAST_CTL Miscellaneous Control MISC_CTL http://www.motorola.com/computer/literature 4-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 280 Universe II (VMEbus to PCI) Chip Table 4-1. Universe II Register Map (Continued) Offset Register Name Miscellaneous Status MISC_STAT User AM Codes Register USER_AM 410 - EFC Universe II Reserved VMEbus Slave Image 0 Control VSI0_CTL VMEbus Slave Image 0 Base Address Register VSI0_BS VMEbus Slave Image 0 Bound Address Register VSI0_BD...
Page 281 VMEbus CSR Base Address Register VCSR_BS Register space marked as “Reserved” should not be overwritten. Unimplemented registers return a value of 0 on reads; writes complete normally. Caution http://www.motorola.com/computer/literature 4-13 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 282: Introduction
PIB. The Hawk ASIC supports eight external PCI masters. This includes Hawk and 7 external PCI masters. The arbitration assignments on the MVME2400 series when the Hawk is the PCI arbiter are as follows: Table 5-1. Hawk Arbitration Assignments PCI Bus Request...
Page 283: Interrupt Handling
Programming Details Interrupt Handling The interrupt architecture of the MVME2400 series SBC is shown in the following figure: INT_ Processor (8529 Pair) MCP_ Hawk MPIC INT_ Processor SERR_& PERR_ PCI Interrupts MCP_ ISA Interrupts 11559.00 9609 Figure 5-1. MVME2400 Series Interrupt Architecture Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ...
Page 284: Hawk Mpic
PIB. The output of the PIB then goes through the MPIC in the Hawk. Refer Chapter 2, Hawk PCI Host Bridge & Multi-Processor Interrupt Controller for details on the MPIC. The following table shows the interrupt assignments for the MPIC on the MVME2400 series: Table 5-2. MPIC Interrupt Assignments MPIC Edge/...
Page 285: 8259 Interrupts
Programming Details Notes 1. Interrupt from the PCI/ISA Bridge. 2. The mapping of interrupt sources from the VMEbus and Universe II internal interrupt sources is programmable via the Local Interrupt Map 0 Register and the Local Interrupt Map 1 Register in the Universe II ASIC.
Page 286: Figure 5-2. Pib Interrupt Handler Block Diagram
Control Register IRQ9 IRQ10 IRQ11 Controller 2 PIRQ3_ IRQx (INT2) IRQ12 PIRQ Route Control Register IRQ13 IRQ14 IRQ15 1897 9609 Figure 5-2. PIB Interrupt Handler Block Diagram http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 287: Table 5-3. Pib Pci/Isa Interrupt Assignments
Programming Details The assignments of the PCI and ISA interrupts supported by the PIB are as follows: Table 5-3. PIB PCI/ISA Interrupt Assignments Edge/ Interrupt Source Notes Level IRQ0 INT1 Edge High Timer 1 / Counter 0 IRQ1 Not used 3-10 IRQ2 Edge...
Page 288: Isa Dma Channels
ISA DMA Channels The MVME2400 series does not implement any ISA DMA channels. Exceptions Sources of Reset There are nine potential sources of reset on the MVME2400 series. They are: 1. Power-On Reset 2. RESET Switch 3. Watchdog Timer Reset via the MK48T59 Timekeeper device 4.
Page 289: Soft Reset
Programming Details The following table shows which devices are affected by various reset sources: Table 5-4. Reset Sources and Devices Affected Device Affected Power-On Reset Switch Watchdog (MK48T59) VME System Reset (SYSRESET# Signal) VME System Software Reset (MISC_CTL Register) VME Local Software Reset (MISC_CTL Register) VME CSR Reset (VCSR_SET Register) Hot Reset (Port 92 Register)
Page 290: Error Notification And Handling
MPIC interrupts or Machine Check Interrupt. Note that the TEA* signal is not used at all by the MVME2400 series. The following table summarizes how the hardware errors are handled by the MVME2400 series: Table 5-5.
Page 291: Endian Issues
Endian software. Because the PowerPC processor is inherently Big- Endian, PCI is inherently Little-Endian, and the VMEbus is Big-Endian, things do get rather confusing. The following figures shows how the MVME2400 series handles the Endian issue in Big-Endian and Little- Endian modes: 5-10 Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ...
Page 292: Figure 5-3. Big-Endian Mode
60X System Bus Hawk Big-Endian N-way Byte Swap Little-Endian PCI Local Bus Universe II Little-Endian N-way Byte Swap Big-Endian VMEbus 1898 9609 Figure 5-3. Big-Endian Mode http://www.motorola.com/computer/literature 5-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 293: Figure 5-4. Little-Endian Mode
Programming Details Little-Endian PROGRAM Little-Endian Big-Endian EA Modification (XOR) Hawk DRAM 60X System Bus Hawk Big-Endian EA Modification Little-Endian PCI Local Bus Universe II Little-Endian N-way Byte Swap Big-Endian VMEbus 1899 9609 Figure 5-4. Little-Endian Mode 5-12 Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ...
Page 294: Processor/Memory Domain
PCI will operate in Little-Endian mode, regardless of the mode of operation in the processor’s domain. PCI-SCSI The MVME2400 series does not implement SCSI. PCI-Ethernet Ethernet is byte stream oriented with the byte having the lowest address in memory being the first one to be transferred regardless of the endian mode.
Page 295: Pci-Graphics
The effects of byte swapping on Big-Endian software must be considered by Big-Endian software. Note There are no graphics on the MVME2400 series boards. Universe II’s Involvement Since PCI is Little-Endian and the VMEbus is Big-Endian, the Universe II performs byte swapping in both directions (from PCI to VMEbus and from VMEbus to PCI) to maintain address invariance, regardless of the mode of operation in the processor’s domain.
Page 296: Rom/Flash Initialization
SMC’s Rom B Base/Size Register. Table 5-6. ROM/FLASH Bank Default rom_b_rv Default Mapping for FFF00000-FFFFFFFF ROM/FLASH Bank A ROM/FLASH Bank B http://www.motorola.com/computer/literature 5-15 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 297: Table A-1. Vpd Packet Types
AMVME2400 VPD Reference Information Vital Product Data (VPD) Introduction The data listed in the following tables are for general reference information. The VPD identifies board information that may be useful during board initialization, configuration, and verification. VPD Data Definitions The following table describes and lists the currently assigned packet identifiers.
Page 298 MVME2400 VPD Reference Information Table A-1. VPD Packet Types (Continued) Size Description Data Type Notes MPU External Clock Frequency in Hertz (for example, Integer (4-byte) 100,000,000 decimal, etc.). This is also called the local processor bus frequency. Reference Clock Frequency in Hertz (for example, Integer (4-byte) 32,768 decimal, etc.).
Page 299: Vital Product Data (Vpd) Introduction
PCO_PCI1_CONN3 PCI/PMC bus 1 connector 3 present PCO_PCI1_CONN4 PCI/PMC bus 1 connector 4 present PCO_ISA_CONN1 ISA bus connector 1 present PCO_ISA_CONN2 ISA bus connector 2 present http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 300 MVME2400 VPD Reference Information Table A-2. MVME2400 Product Configuration Options Data (Continued) Bit Number Bit Mnemonic Bit Description PCO_ISA_CONN3 ISA bus connector 3 present PCO_ISA_CONN4 ISA bus connector 4 present PCO_EIDE1_CONN1 IDE/EIDE device 1 connector 1 present PCO_EIDE1_CONN2 IDE/EIDE device 1 connector 2 present PCO_EIDE2_CONN1 IDE/EIDE device 2 connector 1 present PCO_EIDE2_CONN2...
Page 301: Vpd Data Definitions - Flash Memory Configuration Data
Manufacturer’s Identifier (FFFF = Undefined/Not- Applicable) FMC_DID Manufacturer’s Device Identifier (FFFF = Undefined/Not- Applicable) FMC_DDW Device Data Width (for example, 8-bits, 16-bits) FMC_NOD Number of Devices/Sockets Present http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 302: Vpd Data Definitions - L2 Cache Configuration Data
MVME2400 VPD Reference Information Table A-3. FLASH Memory Configuration Data Byte Field Field Field Description Offset Size Mnemonic (Bytes) FMC_NOC Number of Columns (Interleaves) FMC_CW Column Width in Bits This will always be a multiple of the device’s data width. FMC_WEDW Write/Erase Data Width The FLASH memory devices must be programmed in...
Page 303 Operation Mode: 00 - Either Write-Through or Write-Back (S/W Configurable) 01 - Either Write-Through or Write-Back (H/W Configurable) 02 - Write-Through Only 03 - Write-Back Only http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 304 MVME2400 VPD Reference Information Table A-4. L2 Cache Configuration Data (Continued) Byte Field Field Mnemonic Field Description Offset Size (Bytes) L2C_ERROR_DETECT Error Detection Type: 00 - None 01 - Parity 02 - ECC L2C_SIZE L2 Cache Size (Should agree with the physical organization above): 00 - 256K 01 - 512K...
Page 305: Table A-5. Vpd Srom Configuration Specification For 01-W3394F01
One MVME2400 board build configuration example is provided below. Table A-5. VPD SROM Configuration Specification for 01-W3394F01* Offset Value Field Type Description 00 (0x00) ASCII Eye-Catcher (“MOTOROLA”) Note: Lowest CRC byte for the calculation of CRC. 01 (0x01) 02 (0x02) 03 (0x03) 04 (0x04) 05 (0x05) 06 (0x06)
Page 306 MVME2400 VPD Reference Information Table A-5. VPD SROM Configuration Specification for 01-W3394F01* (Continued) Offset Value Field Type Description 23 (0x17) 24 (0x18) 25 (0x19) 26 (0x1a) 27 (0x1b) 28 (0x1c) 29 (0x1d) 30 (0x1e) 31 (0x1f) 32 (0x20) 33 (0x21) 34 (0x22) 35 (0x23) 36 (0x24)
Page 307 PACKET MPU External Clock Frequency in Hertz [100 MHz] ASCII 70 (0x46) 71 (0x47) 72 (0x48) 73 (0x49) 74 (0x4A) 75 (0x4B) MPU Type [750] http://www.motorola.com/computer/literature A-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 308 MVME2400 VPD Reference Information Table A-5. VPD SROM Configuration Specification for 01-W3394F01* (Continued) Offset Value Field Type Description 76 (0x4C) 77 (0x4D) 78 (0x4E) 79 (0x4F) 80 (0x50) PACKET EPROM CRC INTEGER When computing the CRC this field (that is, 4 bytes) is set to zero.This CRC only covers the range as Integer (4-byte).
Page 309 L2 Cache Configuration (0x6E) BINARY 111 (0x6F) 112 (0x70) 113 (0x71) 114 (0x72) 115 (0x73) 116 (0x74) 117 (0x75) 118 (0x76) 119 (0x77) 120 (0x78) 121 (0x79) http://www.motorola.com/computer/literature A-13 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 310 MVME2400 VPD Reference Information Table A-5. VPD SROM Configuration Specification for 01-W3394F01* (Continued) Offset Value Field Type Description (0x7A) (0x7B) (0x7C) (0x7D) (0x7E) PACKET Host PCI-Bus Clock Frequency in Hertz [33 MHz] (0x7F) INTEGER 128 (0x80) 129 (0x81) 130 (0x82) 131 (0x83) 132 (0x84) 133 (0x85)
Page 311: Table B-1. Motorola Computer Group Documents
BRelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature.
Page 312: Table B-2. Manufacturers' Documents
Table B-2. Manufacturers’ Documents Document Title and Source Publication Number PowerPC 750 RISC Microprocessor Technical Summary MPC750/D Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com PowerPC 750 RISC Microprocessor User’s Manual MPC750UM/AD...
Page 313 Table B-2. Manufacturers’ Documents (Continued) Document Title and Source Publication Number PowerPC Microprocessor Family: The Programming Environments MPCFPE/AD Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com IBM Microelectronics Mail Stop A25/862-1 MPRPPCFPE-01...
Page 314: Related Specifications
Related Documentation Table B-2. Manufacturers’ Documents (Continued) Document Title and Source Publication Number M48T559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet M48T59 SGS-Thomson Microelectronics Group Marketing Headquarters (or nearest Sales Office) 1000 East Bell Road Phoenix, Arizona 85022 Telephone: (602) 867-6100 Universe II User Manual Universe (Part Number...
Page 315: Table B-3. Related Specifications
IEEE - Common Mezzanine Card Specification (CMC) P1386 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 http://www.motorola.com/computer/literature Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 316 Related Documentation Table B-3. Related Specifications (Continued) Document Title and Source Publication Number IEEE - PCI Mezzanine Card Specification (PMC) P1386.1 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 Peripheral Component Interconnect (PCI) Local Bus Specification, PCI Local Bus...
Page 317 Document Title and Source Publication Number PowerPC Microprocessor Common Hardware Reference Platform A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com AFDA, Apple Computer, Inc. P. O. Box 319...
Page 318 Please note that, while these URLs have been verified, they are subject to change without notice. Motorola Computer Group, http://www.motorola.com/computer Motorola Computer Group OEM Services, http://www.motorola.com/computer/support Computer Group Literature Center Web Site Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 319 Index Numerics to PCI Slave 2-23 addressing mode 16550 access registers 1-25 for PCI Master 2-28 16550 UART 1-25 PCI Slave limits 2-24 32-Bit Counter 3-71 Application-Specific Integrated Circuit 3-71 (ASIC) 8259 interrupts arbiter as controlled by the XARB register 2-16 Hawk’s internal 2-34...
Page 320 Index Hawk with SDRAMs contention board configuration information 1-23 between PCI and PPC 2-44 bridge contention handling PHB viii, explained (PHB) 2-45 PowerPC to PCI Local Bus Bridge viii, control bit descriptions 3-38 control bit, definition bus cycle types conventions, manual on the PCI bus 2-30 Critical Word First (CWF)
Page 321 End-of-Interrupt Registers 2-122 explained Error Address Register Flash (see ROM/Flash) 3-17 3-50 four-beat reads/writes error correction 3-15 functional description Error Correction Codes 3-86 Hawk PHB http://www.motorola.com/computer/literature IN-3 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 322 Index interrupts Universe II Hawk MPIC control registers 2-22 Hawk’s DEVSEL_ pin General Control Register as criteria for PHB config. mapping 2-19 3-40 Hawk’s I2C bus 3-76 General Control-Status/Feature Registers Hawk’s PCI arbiter 2-69 priority schemes 2-35 general information Hawk’s SMC Universe II overview General Purpose Registers...
Page 323 1-31 endian issues 5-10 Location Monitor Upper Base Address Reg- interrupt handling ister 1-30 sources of reset Lock Resolution MVME2400 description programmable 2-46 MVME2400 series http://www.motorola.com/computer/literature IN-5 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 324 Index programmable registers PCI master command codes 2-27 MVME240x features PCI memory maps 1-12 MVME2600 series interrupt architecture PCI PREP memory map 1-15 PCI registers 2-91 PCI request negation, definition speculative 2-47 NVRAM/RTC & Watchdog Timer Registers PCI Slave 1-26 disconnect scenarios 2-24 with PCI Master...
Page 325 PPC Bus Address Space 2-19 processor/memory domain PPC bus arbiter 2-15 MPC604 5-13 PPC Bus features product overview - features PPC Bus Interface Universe II http://www.motorola.com/computer/literature IN-7 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 326 Index Programmable Lock Resolution 2-46 Header Type 2-95 programming details Interprocessor Interrupt Dispatch 2-120 programming model Interrupt Acknowledge 2-121 programming ROM/Flash devices 3-74 Interrupt Task Priority 2-120 IPI Vector/Priority (MPIC) 2-111 MPIC 2-104 RAM A BASE 3-43, 3-66 MPIC I/O Base Address 2-96 RAM B BASE 3-43, 3-66...
Page 327 SDRAM Attributes Register ROM/Flash A size encoding 3-54 3-41 ROM/Flash A Width control bit 3-54 SDRAM Base Address Register ROM/Flash B Base Address control bits 3-56 http://www.motorola.com/computer/literature IN-9 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 328 Index 3-66 ECC Control Register 3-45 SDRAM Base Address/Enable 3-76 Error Address Register 3-50 SDRAM Base Register error correction 3-15 3-43 Error Logger Register 3-49 SDRAM block organization error logging 3-17 SDRAM Control Registers External Register Set 3-34 Initialization Example 3-77 General Control Register 3-40...
Page 329 Geographical Address Register compelled (VGAR) 1-32 PCI originated/PPC bound described VME Registers 1-27 posted VME registers 1-27 PPC originated/PCI bound described VMEbus PPC Slave limits http://www.motorola.com/computer/literature IN-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
Page 330 Index master mapping diagram 1-19 slave mapping diagram 1-21 VMEbus domain in endian issues 5-14 VMEbus interface to Universe II VMEbus interrupt handling VMEbus mapping 1-18 VMEbus master map 1-18 VMEbus slave map 1-20 VMEbus slave map example 1-23 Universe II PCI Register Values 1-22 example of SROM data use of...
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Motorola MVME2400 Series Programmer's Reference Manual

About this Manual

CHAPTER 1 Board Description and Memory Maps

CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

CHAPTER 3 System Memory Controller (SMC)

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Summary of Contents for Motorola MVME2400 Series