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Motorola MCPN750A Installation And Use Manual
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Motorola MCPN750A Installation And Use Manual

Motorola MCPN750A Installation And Use Manual

Compactpci single board computer
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  • Page 1 (217) 352-9330 | Click HERE Find the Emerson / Motorola MCPN750 at our website:...
  • Page 2 MCPN750A CompactPCI Single Board Computer Installation and Use MCPN750A/IH5 September 2001 Edition...
  • Page 3 All Rights Reserved. Printed in the United States of America. Motorola and the stylized M logo are registered trademarks of Motorola, Inc. PowerPC is a registered trademark of International Business Machines and is used by Motorola Inc. under license from IBM Corporation.
  • Page 4 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
  • Page 5 Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
  • Page 6 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 7 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.

  • Page 8: Table Of Contents

    COM 1 and COM 2 Asynchronous Serial Ports........1-18 COM3 and COM4 Asynchronous Serial Ports..........1-20 Hardware Installation....................1-21 Installing PMC Modules on the MCPN750A SBC ..........1-21 Installing the MCPN750A Baseboard ..............1-24 Installing a TMCPN710 or TM-PIMC-0001 Transition Module .....1-26 Installing PIMs on the TM-PIMC-0001 Transition Module .....1-26 Installing the Transition Module in the Chassis ........1-28...
  • Page 9 CHAPTER 2 Startup and Operation Introduction ....................... 2-1 Applying Power ......................2-1 Memory Maps......................2-3 Processor Memory Map ..................2-3 Default Processor Memory Map ..............2-3 PCI Local Bus Memory Map ................2-4 CompactPCI Memory Map ................2-5 Address Decoding with the 21554 .............. 2-5 L2 Cache......................
  • Page 10 CHAPTER 4 CNFG and ENV Commands Overview........................4-1 CNFG - Configure Board Information Block ............4-2 ENV - Set Environment .....................4-3 Configuring the PPCBug Parameters ..............4-3 CHAPTER 5 Remote Start Via the PCI Bus Introduction........................5-1 Overview......................5-1 Command/response Register Description............5-3 Opcode 0x01: Write/Read Virtual Register ............5-5 Opcode 0x02: Initialize Memory ................5-5 Opcode 0x03: Write/Read Memory..............5-6 Opcode 0x04: Checksum Memory ..............5-6...
  • Page 11 MCPN750A and Transition Module Connectors ............7-1 MCPN750A Connector Pin Assignments ..............7-2 MCPN750A CompactPCI Bus Connectors (J1/J2)..........7-2 MCPN750A CompactPCI User I/O Connector J3 ..........7-4 MCPN750A Connector J4.................. 7-6 MCPN750A CompactPCI User I/O Connector (J5) .......... 7-7 MCPN750A PCI Mezzanine Card Connectors (J11/21, J12/22, J13/23, J14/24 ................
  • Page 12 TM-PIMC-0001 Transition Module IDE Compact FLASH Connector (J1)..7-31 TM-PIMC-0001 Transition Module PMC I/O Connectors (J10, J20, and J14/J24)..................7-33 APPENDIX A Specifications Specifications ......................A-1 Cooling Requirements ....................A-2 EMC Compliance......................A-3 APPENDIX B Related Documentation Motorola Computer Group Documents ..............B-1 Manufacturers’ Documents..................B-2 Related Specifications....................B-4...
  • Page 14 List of Figures Figure 1-1. MCPN750A Base Board Block Diagram..........1-2 Figure 1-2. MCPN750A Switches, Headers, Connectors, Fuses, LEDs ....1-9 Figure 1-3. TMCPN710 Connector and Header Locations ........1-12 Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 and 2 ........1-14 Figure 1-5. TMCPN710 Serial Ports 3 and 4............1-15 Figure 1-6.
  • Page 16 Table 6-2. Multiplexing Sequence of the MX Function ..........6-18 Table 7-1. MCPN750A J1 CompactPCI Connector ..........7-2 Table 7-2. MCPN750A J2 CompactPCI Connector ..........7-3 Table 7-3. MCPN750A J3 User I/O Connector ............7-5 Table 7-4. MCPN750A J5 User I/O Connector ............7-7 Table 7-5. MCPN750A PCI Mezzanine Card Connector ..........7-9 Table 7-6.
  • Page 17 Table 7-25. PMC I/O Modules 1 and 2 (PIM1 and PIM2) - PMC I/O Connector Pin Assignments..............7-36 Table A-1. MCPN750 Specifications ..............A-1 Table B-1. Motorola Computer Group Documents ..........B-1 Table B-2. Manufacturers’ Documents ..............B-2 Table B-3. Related Specifications ................B-4...
  • Page 18 MCPN750A family of Single Board Computers. In addition, sufficient information is also provided for the two transition modules manufactured by Motorola for use with the MCPN750A (TMCPN710 and TM-PIMC- 0001). The document should be used by anyone who wants general, as well as technical information about the MCPN750A products.

  • Page 19: Summary Of Changes

    Previously listed model numbers. preceeding this section. Reinserted information left out of IH4 version of manual, which included information on MCPN750A, the TMCPN710 and the TM-PIMC-0001, instead of the earlier MCPN750. Also, included J8 jumper settings for Stand- Alone operation.

  • Page 20: Comments And Suggestions

    EMC compliance. Appendix B, Related Documentation, provides a listing of related motorola and vendor documentation, as well as a list of related industry standard specifications. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation.

  • Page 21: Conventions Used In This Manual

    In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

  • Page 22: Introduction

    TMCPN710 or the TM-PIMC-0001 for added I/O flexibility Product Description The MCPN750A is a hot swappable CompactPCI, non-system slot, single board computer based on the PowerPlus architecture. It consists of the MPC750 processor with L2 cache, the Raven PCI Bridge and Interrupt...

  • Page 23: Figure 1-1. Mcpn750A Baseboard Block Diagram

    33MHz 32/64-bit PCI Local Bus Ethernet PCI-PCI BRIDGE Intel 21143 VT82C586B Intel 21554 Registers 10BT/ 100BTx NVRAM/ WD/RTC MK48T559 RS232 UARTs 16C550C IOMX User I/O J3 & J5 CompactPCI J1/J2 Figure 1-1. MCPN750A Baseboard Block Diagram Computer Group Literature Center Web Site...

  • Page 24: Getting Started

    Getting Started This section provides an overview of the steps necessary to install and power up the MCPN750A, any additional equipment requirements, and a brief section on unpacking and ESD precautions. As identified in the table below, several steps can be omitted if your board, for example, has been...

  • Page 25: Equipment Required

    Programmer’s Reference Guide, listed in Appendix B, Related Documentation. Equipment Required The following equipment is required to complete an MCPN750A system: CompactPCI system enclosure System console terminal Operating system (and/or application software) Disk drives (and/or other I/O) and controllers...

  • Page 26: Unpacking Instructions

    Caution ESD Precautions Motorola strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system. Electronic components, such as disk drives, computer boards, and memory modules, can be extremely sensitive to ESD. After removing the component from the system or its protective wrapper, place the component flat on a grounded, static-free surface (and in the case of a board, component side up).

  • Page 27: Preparation

    The MCPN750A control registers are described in the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG), which can be accessed on line in pdf or html format through the Motorola Computer Group Literature web site (http://www.motorola.com/computer/literature).
  • Page 28 Preparation The MCPN750A is factory tested and shipped with the configurations described in the following sections. The MCPN750A’s required and factory-installed debug monitor, PPCBug, operates with those factory settings. Flash Bank Selection (J7) The MCPN750A baseboard has provision for 1MB of 16-bit Flash memory and 4MB of linear Flash memory.
  • Page 29 Stand-Alone Operating Mode (J8) The MCPN750A has a stand-alone operating mode that allows the MCPN750A to function without the clock from the system slot controller board. Installing a jumper across pins 1 and 2 of J8 enables the stand-alone mode. The J8 jumper must be removed for normal operation.

  • Page 30: Figure 1-2. Mcpn750A Switches, Headers, Connectors, Fuses, Leds

    Preparation BFL CPU ABT/RST Figure 1-2. MCPN750A Switches, Headers, Connectors, Fuses, LEDs http://www.motorola.com/computer/literature...

  • Page 31: System Considerations

    In the standard operating mode (with a system slot board), the system slot board is used to provide clock and arbitration signals to the MCPN750A. In the stand-alone mode, a jumper must be set on the MCPN750A, in order to obtain clock signals from other on-board devices.

  • Page 32: Tmcpn710 Transition Module Preparation

    Preparation TMCPN710 Transition Module Preparation The TMCPN710 transition module (Figure 1-3) is used in conjunction with all models of the MCPN750A baseboard: The features of the TMCPN710 include: Two EIA-232-D asynchronous serial ports (identified as COM1 on the transition module panel)

  • Page 33: Figure 1-3. Tmcpn710 Connector And Header Locations

    Hardware Preparation and Installation Figure 1-3. TMCPN710 Connector and Header Locations 1-12 Computer Group Literature Center Web Site...

  • Page 34: Serial Ports 1 And 2

    COM1 on the processor board, connect pins 1-2 of J7. Serial Port 1 jumper settings (factory configuration) Enable COM1 on TMCPN710 Enable COM1 on MCPN750A Note If the J7 jumper is not present on the TMCPN710, the board automatically enables COM1 on the MCPN750A. http://www.motorola.com/computer/literature 1-13...
  • Page 35 Hardware Preparation and Installation MCPN750A RJ45 COM1 (front panel) TMCPN710 COM1 (rear panel) 16C550 SOUT 16C550 COM2 (rear panel) SOUT 2362 9808 Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 and 2 1-14 Computer Group Literature Center Web Site...

  • Page 36: Com3 And Com4 Asynchronous Serial Ports

    COM3 and COM4 Asynchronous Serial Ports The signals for COM3 and COM4 serial ports are routed to headers on the TMCPN710 Transition Module. These headers are intended for debug purposes only. Figure 1-5 depicts this configuration. MCPN750A TMCPN710 16C550 SOUT...

  • Page 37: Tm-Pimc-0001 Transition Module Preparation

    Hardware Preparation and Installation TM-PIMC-0001 Transition Module Preparation The TM-PIMC-0001 transition module (Figure 1-6) is used in conjunction with all models of the MCPN750A baseboard. The features of this transition module include: Connections for two single wide, or one double wide PIM card.

  • Page 38: Figure 1-6. Tm-Pimc-0001 Connector And Header Locations

    Preparation Figure 1-6. TM-PIMC-0001 Connector and Header Locations http://www.motorola.com/computer/literature 1-17...

  • Page 39: Com1 And Com2 Asynchronous Serial Ports

    PIM 1 on the transition module. Jumper J2 on the transition module must be configured in the same way for the COM2 port. Serial Port 1 jumper settings Enable COM1 for PIM1 Enable COM1 on MCPN750A of TM-PIMC-0001 Serial Port 2 jumper settings Enable COM2 for PIM2...
  • Page 40 Preparation TM-PIMC-0001 MCPN750 RJ45 PIM 1 COM1 (front panel) COM1 (rear panel) 16C550 SOUT 16C550 COM2 (rear panel) SOUT PIM 2 2362 0001 Figure 1-7. MCPN750A/TM-PIMC-0001 Serial Ports 1 and 2 http://www.motorola.com/computer/literature 1-19...

  • Page 41: Com3 And Com4 Asynchronous Serial Ports

    The signals for COM3 and COM4 serial ports are routed to 10-pin headers on the TM-PIMC-0001 Transition Module (J12 and J13). These headers function as I/O connectors for the MCPN750A and are permanently configured as DTE. Figure 1-8 depicts this configuration.

  • Page 42: Hardware Installation

    MCPN750A, ensure that all header jumpers are configured as desired. In most cases, PMC modules ordered with the baseboard are installed on the MCPN750A at the factory and the order is shipped as a single unit. The user-configured jumpers on the PMCs are accessible with the mezzanines installed.

  • Page 43: Figure 1-9. Pmc Module Placement On Mcpn750A

    Figure 1-9. PMC Module Placement on MCPN750A Inserting or removing modules in a non-hot swap chassis with power applied may result in damage to module components. The MCPN750A is a hot swappable board and may be inserted in a hot swap chassis, such as Caution a CPX2000 or a CPX8000 series chassis with power applied.
  • Page 44 Caution 5. Remove the PMC filler from the front panel of the MCPN750A. 6. Slide the edge connector of the PMC module into the front panel opening from behind and place the PMC module on top of the baseboard.

  • Page 45: Installing The Mcpn750A Baseboard

    CompactPCI modules. Inserting or removing modules in a non-hot swap chassis with power applied may result in damage to module components. The MCPN750A is a hot swappable board and may be inserted in a hot swap chassis such as a Caution CPX2000, or a CPX8000 series chassis with power applied.
  • Page 46 Avoid touching areas of integrated circuitry; static discharge can damage these circuits Caution 6. Secure the MCPN750A in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions. 7. Replace the chassis or system cover(s), making sure no cables are pinched.

  • Page 47: Installing A Tmcpn710 Or Tm-Pimc-0001 Transition Module

    Installing a TMCPN710 or TM-PIMC-0001 Transition Module The TMCPN710 or TM-PIMC-0001 Transition Module may be required to complete the configuration of your particular MCPN750A system. If so, perform the following install steps to install this board. For more detailed information on the TMCPN710 or TM-PIMC-0001 Transition Module refer to the corresponding users guide, i.e., TMCPN710 Transition Module...
  • Page 48 The TM-PIMC- 0001 is not a hot swap board, but it may be installed in a hot swap chassis Caution with power applied, if the corresponding MCPN750A is removed before the TM-PIMC-0001 board is installed. http://www.motorola.com/computer/literature...

  • Page 49: Installing The Transition Module In The Chassis

    9. Replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on, or if hot swapping, you may now install the MCPN750A. Installing the Transition Module in the Chassis 1.
  • Page 50 Caution 3. With the TMCPN710 or TM-PIMC-0001 in the correct vertical position that matches the pin positioning of the corresponding MCPN750A board carefully slide the transition module into the appropriate slot and seat tightly into the backplane. Refer to Figure 1-11.
  • Page 51 Hardware Preparation and Installation MCPN750A TMCPN710 TM-PIMC-0001 Figure 1-11. TMCPN710 or TM-PIMC-0001/MCPN750A Mating Configuration 1-30 Computer Group Literature Center Web Site...

  • Page 52: Mcpn750A Module Power Requirements

    MCPN750A Module Power Requirements MCPN750A Module Power Requirements The MCPN750A board draws +5V, +3.3V and VIO power from the J1 connector. The +12V and -12V voltages are monitored by the MCPN750A hot swap controller and provided for use by the PMCs and transition modules.
  • Page 53 Hardware Preparation and Installation 1-32 Computer Group Literature Center Web Site...

  • Page 54: Introduction

    2Startup and Operation Introduction This chapter supplies information for use of the MCPN750A family of Single Board Computers in a system configuration. Here you will find the power-up procedure and descriptions of the switches and LEDs, memory maps, and software initialization.

  • Page 55: Figure 2-1. Ppcbug System Startup

    AUTOBOOT (IF ENABLED) OPERATING SYSTEM 11734.00 9702 Figure 2-1. PPCBug System Startup The MCPN750A front panel has one switch and three LED ABORT RESET (light-emitting diode) status indicators ( and HOT SWAP STATUS For more information on front panel operation refer to Chapter 6, Functional Description.

  • Page 56: Memory Maps

    The following sections give a general description of the MCPN750A memory organization from the above three points of view. Detailed memory maps can be found in the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG). Processor Memory Map The processor memory map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set.

  • Page 57: Pci Local Bus Memory Map

    The local PCI memory map is the PCI memory map as viewed by the MCPN750A base board. This is also the secondary bus side of the 21554 on the MCPN750A. This map is controlled by the Raven ASIC and the 21554 PCI-to-PCI bridge.

  • Page 58: Compactpci Memory Map

    PCI-to-PCI bridges in that it uses address translation instead of a flat address map between primary and secondary PCI buses. In the MCPN750A configuration, the primary bus is the CompactPCI bus and the secondary bus is the MCPN750A local bus.

  • Page 59: L2 Cache

    Startup and Operation L2 Cache The MCPN750A SBC uses a backside L2 cache structure via the MPC750 processor chip. The MPC750 L2 cache is implemented with an onchip 2- way set-associative tag memory and external direct-mapped synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated 72-bit wide (64 bits of data and 8 bits of parity) L2 cache port.
  • Page 60 There are four programmable map decoders for each direction to provide flexible address mappings between the PPC/DRAM and the PCI Local Bus. Refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG) for additional information and programming details.

  • Page 61: Pci Arbitration

    Peripheral Bus Controller (PBC). The output of the PBC then goes through the MPIC in Raven. Since the MCPN750A board is designed to support processor data bus parity, the Raven uses some of the pins normally used as external interrupt inputs as parity pins.

  • Page 62: Isa Dma Channels

    The ISA bus (interrupts from ISA devices) The ISA interrupts are handled as a single 8259 interrupt from the VT82C586B PBC device. For details on interrupt handling, refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG). ISA DMA Channels The PBC supports seven 8237 compatible DMA channels.

  • Page 63: Table 2-2. Classes Of Reset And Effectiveness

    21554 data buffers. * A configuration write is required to clear the Secondary Reset Bit after it has been written so this bit must not be set by the local MCPN750A processor or else the board will lock up.

  • Page 64: Power-On Reset

    Undervoltage Reset The MCPN750A SBC generates a hard reset when the Hot Swap power control chip (LTC1643) detects a supply voltage +5V, +3.3V, +12V or - 12V fall below minimum thresholds of +4.75V, +3.135V, +10.8 and -10.8 volts respectively.

  • Page 65: Software Resets

    21554 Bridge Control register from the PCI address space. This allows the System Slot processor to do a software controlled reset of the MCPN750A SBC. Refer to the Intel 21554 Data Sheet for details.

  • Page 66: Pci Domain

    Since the Raven maintains address invariance in both little-endian and big- endian mode, no endian issues should arise for Ethernet data. Big-endian software must still take the byte-swapping effect into account when accessing the registers of the PCI/Ethernet device, however. http://www.motorola.com/computer/literature 2-13...
  • Page 67 Startup and Operation 2-14 Computer Group Literature Center Web Site...

  • Page 68: Ppcbug Overview

    Related Documentation appendix. PPCBug Basics The PowerPC debug firmware, PPCBug, is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation.
  • Page 69 PPCBug Firmware Package User’s Manual. It is hereafter referred to as “the debugger” or “PPCBug”. A command-driven diagnostics package for the MCPN750A hardware, hereafter referred to as “the diagnostics.” The diagnostics package is described in the PPCBug Diagnostics Manual.

  • Page 70: Memory Requirements

    MPU, Hardware, and Firmware Initialization The debugger performs the MPU, hardware, and firmware initialization process. This process occurs each time the MCPN750A is reset or powered up. The steps below are a high-level outline; not all of the detailed steps are listed.
  • Page 71 PPCBug 7. Calculate the external bus clock speed of the MPU. 8. Delays for 750 milliseconds. 9. Determines the CPU board type. 10. Sizes the local read/write memory (i.e., DRAM). 11. Initializes the read/write memory controller. 12. Sets base address of memory to $00000000. 13.

  • Page 72: Using Ppcbug

    PPC1-Bug appears on the screen, the debugger is ready to accept debugger commands. When the prompt appears on the screen, the PPC1-Diag debugger is ready to accept diagnostic commands. To switch from one mode to the other, enter SD. http://www.motorola.com/computer/literature...

  • Page 73: Debugger Commands

    PPCBug What you key in is stored in an internal buffer. Execution begins only after you press the Return or Enter key. This allows you to correct entry errors, if necessary, with the control characters described in the PPCBug Firmware Package User’s Manual, Chapter 2. After the debugger executes the command, the prompt reappears.

  • Page 74: Table 3-1. Debugger Commands

    Configure Board Information Block Checksum CSAR PCI Configuration Space READ Access CSAW PCI Configuration Space WRITE Access Data Conversion Block of Memory Move One Line Disassembler Dump S-Records ECHO Echo String Set Environment FORK Fork Idle MPU at Address http://www.motorola.com/computer/literature...
  • Page 75 PPCBug Table 3-1. Debugger Commands (Continued) Command Description FORKWR Fork Idle MPU with Registers Go Direct (Ignore Breakpoints) GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Variable(s) Dump GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable(s) Display Go to Next Instruction...
  • Page 76 Printer Detach PBOOT Bootstrap Operating System Port Format NOPF Port Detach PFLASH Program FLASH Memory Put RTC into Power Save Mode ROMboot Enable NORB ROMboot Disable Register Display REMOTE Remote RESET Cold/Warm Reset Read Loop Register Modify Register Set http://www.motorola.com/computer/literature...

  • Page 77: Diagnostic Tests

    Although a command to allow the erasing and reprogramming of Flash memory is available to you, keep in mind that reprogramming any portion of the MCPN750A baseboard’s Flash memory (Bank B) will erase Caution everything currently contained in the baseboard Flash, including the PPCBug debugger.

  • Page 78: Table 3-2. Diagnostic Test Groups

    PPC1-Diag> displays, and all of the debugger and diagnostic commands are available. Note that not all tests are valid for the MCPN750A. Using the HE command, you can list the diagnostic routines available in each test group. Refer to the PPCBug Diagnostics Manual for complete descriptions of the diagnostic routines and instructions on how to invoke them.
  • Page 79 Refer to the documentation on a particular diagnostic for the correct mode. Test Sets marked with an asterisk (*) are not available on the MCPN750A, unless SCSI or Video PMCs are installed. 3-12 Computer Group Literature Center Web Site...

  • Page 80: Overview

    4CNFG and ENV Commands Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the PowerPC board’s Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM). The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware.

  • Page 81: Cnfg - Configure Board Information Block

    The data strings are padded with zeroes if the length is not met. *Note: the MCPN750A has no local SCSI bus controller, hence, the Local SCSI Identifier parameter is ignored by the PPCBug.

  • Page 82: Env - Set Environment

    Probe System for Supported I/O Controllers [Y/N] = Y? Accesses will be made to the appropriate system buses (e.g., VMEbus, local MPU bus) to determine the presence of supported controllers. (Default) Accesses will not be made to the VMEbus to determine the presence of supported controllers. http://www.motorola.com/computer/literature...
  • Page 83 Secondary SCSI Identifier = “07”? If the board has a secondary SCSI controller, this number is the secondary SCSI ID or address. For the MCPN750A, all PCI add-on SCSI controllers/adapters supported by PPCBug are set to the SCSI ID value entered here.
  • Page 84 Auto Boot Enable [Y/N] = N? The Autoboot function is enabled. The Autoboot function is disabled. (Default) Auto Boot at power-up only [Y/N] = N? Autoboot is attempted at power-up reset only. Autoboot is attempted at any reset. (Default) http://www.motorola.com/computer/literature...
  • Page 85 CNFG and ENV Commands Auto Boot Scan Enable [Y/N] = Y? If Autoboot is enabled, the Autoboot process attempts to boot from devices specified in the scan list (e.g., ). (Default) FDISK/CDROM/TAPE/HDISK If Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot.
  • Page 86 Network Auto Boot Enable [Y/N] = N? The Network Auto Boot (NETboot) function is enabled. The NETboot function is disabled. (Default) Network Auto Boot at power-up only [Y/N] = N? NETboot is attempted at power-up reset only. NETboot is attempted at any reset. (Default) http://www.motorola.com/computer/literature...
  • Page 87 CNFG and ENV Commands Network Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of network controller modules currently supported by PPCBug. (Default = $00) Network Auto Boot Device LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of network controller modules currently supported by PPCBug.
  • Page 88 ROM Next Access Length (0 - 15) = 0? The value programmed into the MPC105 “ROMNAL” field (Memory Control Configuration Register 8: bits 28-31) to represent wait states in access time for nibble (or burst) mode ROM accesses. The lowest http://www.motorola.com/computer/literature...
  • Page 89 PIRQ0/1/2/3. The default is determined by system type. For details on PCI/ISA interrupt assignments and for suggested values to enter for this parameter, refer to the 8259 Interrupts section of Chapter 4 in the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide. Serial Startup Code Master Enable [Y/N]=N?
  • Page 90 During this delay, you may press any key to prevent the execution of the startup command buffer. The default value of this parameter causes a startup delay of 5 seconds. http://www.motorola.com/computer/literature 4-11...
  • Page 91 CNFG and ENV Commands Firmware Command Buffer [‘NULL’ terminates entry]? The Firmware Command Buffer contents contain the BUG commands which are executed upon firmware startup. BUG commands you will place into the command buffer should be typed just as you enter the commands from the command line.

  • Page 92: Introduction

    Note Applications may also be downloaded to the MCPN750A via one of the PCI bus windows provided by the PCI-to-PCI bridge. This method is faster than using the PPCBug remote interface and may be preferable to use for large downloads.
  • Page 93 Remote Start Via the PCI Bus A command data and result field. This field provides the data, if any, needed by the command and provides the response from PPCBug upon command completion. The meaning of the bits in this field are specific to each command opcode.

  • Page 94: Command/Response Register Description

    0 upon command completion. If the command fails, it will be written with the value 1. Additional command specific error status may be returned in other fields of the register. (register description continues...) http://www.motorola.com/computer/literature...
  • Page 95 Remote Start Via the PCI Bus Bits 9 to 15 7 bit command option field. Each command specifies the particular meaning of each of the command option bits. Option bits which are unused are considered reserved and should be written to 0 to ensure compatibility with future implementations of this interface.

  • Page 96: Opcode 0X01: Write/Read Virtual Register

    Data field. Note This command does not guarantee that the memory is initialized using any particular ordering or alignment. Do not use it to initialize any area of memory that has alignment or ordering requirements (e.g., device registers). http://www.motorola.com/computer/literature...

  • Page 97: Opcode 0X03: Write/Read Memory

    Remote Start Via the PCI Bus Opcode 0x03: Write/Read Memory This command allows the host to Read or Write individual address locations on the local address bus. Data sizes of 8, 16 and 32 bits are supported. The specific operation and size are determined by the command options field.

  • Page 98: Opcode 0X05: Memory Size Query

    This command allows the host to cause the local CPU to transfer control to a specific execution address on the card. VR0 contains the address to begin execution at. VR2 contains the value that is loaded into CPU register R3 when control is transferred to the execution address. http://www.motorola.com/computer/literature...

  • Page 99: Command/Response Channel Error Codes

    Remote Start Via the PCI Bus The state of CPU registers R0 through R2, and R4 through R31 are indeterminate when control is passed to the address. Note: this command does not return. The OWN flag bit remains clear. Command/Response Channel Error Codes These are the 16 bit values that the target board returns in the Data/Result field of the Command/Response register when the target board detects an error in the processing of a host command.

  • Page 100: Demonstration Of The Host Interface

    The following example demonstrates the use of PPCBug’s Remote Start capability in a CPCI system. In this example, a simple program is loaded into the local memory of a (non-system) target board, the MCPN750A. The CPCI system host board (an MCP750) then uses the PCI Remote Start interface to initiate execution of the program by the target board.
  • Page 101 Remote Start Via the PCI Bus 00040100 0B? .<cr> PPC1-Bug> Enter the program to be executed by the target MPU in the target board’s local memory. MCPN750A (target) Console PPC1-Bug>m 40200;di<cr> 00040200 39400026 syscall .pcrlf<cr> 00040208 39400024 syscall .writeln<cr> 00040210 39400026 syscall .pcrlf<cr>...
  • Page 102 8000EFC4 00000007? .<cr> PPC1-Bug> The result of remote program execution can be viewed on the target console: MCPN750A (target) Console PPC1-Bug> Host wrote 0004 to upper half of VR0 Host wrote 0200 to lower half of VR0 Host wrote 0004 to upper half of VR2...

  • Page 103: Reference Function: Srom_Crc.c

    Remote Start Via the PCI Bus Reference Function: srom_crc.c * srom_crc - generate CRC data for the passed buffer * description: *This function’s purpose is to generate the CRC for thepassed buffer. * call: *argument #1 = buffer pointer *argument #2 = number of elements * return: *CRC data unsigned int...
  • Page 104 Introduction crc_flipped <<= 1; dbit = crc & 1; crc >>= 1; crc_flipped += dbit; crc = crc_flipped ^ 0xffffffff; return (crc & 0xffff); http://www.motorola.com/computer/literature 5-13...
  • Page 105 Remote Start Via the PCI Bus 5-14 Computer Group Literature Center Web Site...

  • Page 106: Functional Description

    6Functional Description Introduction This chapter describes the MCPN750A single-board computer on a block diagram level. The General Description provides an overview of the MCPN750A, followed by a detailed description of several blocks of circuitry. Figure 6-1 shows a block diagram of the overall board architecture.

  • Page 107: General Description

    The processor implements a backside cache controller and the board comes with 1MB of cache memory. As shown in the Features section, the MCPN750A offers many standard features desirable in a CompactPCI computer system such as L2 cache, a...

  • Page 108: Block Diagram

    Block Diagram The MCPN750A interfaces to a CompactPCI bus using a DEC 21554 non- transparent PCI-to-PCI bridge device. This device provides a 64-bit primary and a 64-bit secondary interface allowing full 64-bit data access between CompactPCI bus devices and the host/PCI bridge. The non-...

  • Page 109: Figure 6-1. Mcpn750A Block Diagram

    33MHz 32/64-bit PCI Local Bus Ethernet PCI-PCI BRIDGE Intel 21143 VT82C586B Intel 21554 Registers 10BT/ 100BTx NVRAM/ WD/RTC MK48T559 RS232 UARTs 16C550C IOMX User I/O J3 & J5 CompactPCI J1/J2 Figure 6-1. MCPN750A Block Diagram Computer Group Literature Center Web Site...

  • Page 110: Compactpci Bus Interface

    The secondary bus interfaces to the MCPN750A board local PCI bus, referred to as the local domain or local processor side. The 21554 supports independent primary and secondary address spaces and address translation between the two processor domains.

  • Page 111: Ethernet Interface

    10BaseT/100BaseTX autoselect ethernet interface. The Ethernet interface is routed to an RJ45 connector located at the front panel of the board. The MCPN750A SBC also supports optional routing of the ethernet signals to the J5 connector for ethernet connection on the transition module.

  • Page 112: Pci Mezzanine Interface

    Block Diagram PCI Mezzanine Interface A key feature of the MCPN750A family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus devices (Ethernet, etc.), the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card). This support consists of two single- wide or one double-wide PMC slots.

  • Page 113: Isa Bus Devices

    Functional Description ISA Bus Devices The MCPN750A contains a local ISA bus to provide an interface to ISA compatible devices. The following devices are located on the ISA bus: Four asynchronous serial ports Real-Time Clock & NVRAM & Watchdog Timer...

  • Page 114: Pci Peripheral Bus Controller (Pbc)

    Block Diagram PCI Peripheral Bus Controller (PBC) The MCPN750A uses the VIA Technologies VT82C586B Peripheral Bus Controller (PBC) to supply the interface between the PCI local bus and the ISA, EIDE and USB systems I/O bus (as shown in Figure 6-1 on page 6-4).

  • Page 115: Eide Interface

    ISA Interrupt Controller The PBC contains two 8259 interrupt controllers to support ISA interrupts. The PBC supports programmable interrupt routing and programmable edge or level triggering. Refer to the MCPN750A CompactPCI Single Board Computer Programmers Reference Guide (MCPN750A/PG) for interrupt routing information.

  • Page 116: Real-Time Clock/Nvram/Watchdog Timer Function

    These counters are driven with a 14.31818 MHz clock source. Real-Time Clock/NVRAM/Watchdog Timer Function The MCPN750A employs an SGS-Thomson surface-mount M48T559 RAM and clock chip to provide 8KB of non-volatile static RAM, a real- time clock, and a watchdog timer function. This chip supplies a clock,...

  • Page 117: Replacing Lithium Batteries

    Although the M48T559 is an 8-bit device, 8-, 16-, and 32-bit accesses from the ISA bus to the M48T559 are supported. Refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG) and to the M48T559 Data Sheet for detailed programming and battery life information.
  • Page 118 3. Note the battery polarity and press the new battery into the socket. Note When the battery is in the socket, no soldering is required. 4. Recycle or dispose of the old battery according to local regulations and manufacturer’s instructions. http://www.motorola.com/computer/literature 6-13...

  • Page 119: Hot Swap Control Circuitry

    Functional Description Hot Swap Control Circuitry The MCPN750A provides CompactPCI Hot Swap capability and complies with the CompactPCI Hot Swap Specification (Rev. 1.0). The Hot Swap circuitry supports the process of installing or removing the board without adversely effecting the running system.

  • Page 120: Raven Watchdog Timers

    If the interrupt output is enabled, the Watchdog timer will generate an RTC interrupt if the timer expires. Refer to the device data sheet and the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG) for programming information. http://www.motorola.com/computer/literature...

  • Page 121: Interval Timers

    PBC (this timer output is not used in the MCPN750A). The interval timers use the OSC clock input as their clock source. The MCPN750A drives the OSC pin with a 14.31818 MHz clock source. Serial Port Signal Multiplexing Due to pin limitations of the J3 connector, the MCPN750A multiplexes and de-multiplexes some signals between the MCPN750A board and the TMCPN710 and the TM-PIMC-0001 transition modules.

  • Page 122: I/O Signal Multiplexing (Iomx)

    MXSYNC#, MXDO, and MXDI. MXCLK is the 10 MHz bit clock for the time-multiplexed data lines MXDO and MXDI. MXSYNC# is asserted for one bit time at Time Slot 15 by the MCPN750A board. MXSYNC# is used by the transition module to synchronize with the MCPN750A board.

  • Page 123: Table 6-2. Multiplexing Sequence Of The Mx Function

    Functional Description Table 6-2. Multiplexing Sequence of the MX Function MXDO MXDI (From MCPN750A) (From TMCPN710 & TM-PIMC-0001) TIME SLOT SIGNAL NAME TIME SLOT SIGNAL NAME RTS3 CTS3 DTR3 DSR3 RTS1 DCD3 RTS2 CTS1 RTS4 DTR4 CTS4 Reserved DSR4 Reserved...

  • Page 124: Signal Descriptions

    RTSn - request to send ABORT (ABT)/RESET (RST) Switch (S1) The MCPN750A SBC contains a single push button switch that provides both ABORT and RESET functions. When the switch is depressed for less than 3 seconds, an interrupt is generated to the processor via ISA interrupts IRQ8.

  • Page 125: Front Panel Indicators (Ds1 - Ds3)

    PCI local bus. Flash Memory The MCPN750A base board contains one bank of writeable Boot Flash memory. It consists of two 32-pin PLCC sockets that can be populated with 1MB of FLASH memory. This FLASH memory appears as FLASH Bank B to the Falcon chipset.

  • Page 126: Jtag/Cop

    Flash contents. JTAG/COP Connector J6 on the MCPN750A board provides access to the JTAG/COP interface on the MPC750 processor. The interface can be used to provide debug control and observation of the MPC750. Refer to Table 7-9 for pinout information.

  • Page 127: Ecc Memory Controller

    The Falcon memory controller also provides access to some of the system configuration registers. Refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG) for additional information and programming details.

  • Page 128: Tmcpn710 Transition Module

    The TM-PIMC-0001 transition module is used in conjunction with all models of the MCPN750A base board. The transition module provides additional I/O for the MCPN750A series of SBCs. This transition module also functions as a PMC Interface Module (PIM) carrier, supporting the flexible PIM scheme for PMC rear I/O.
  • Page 129 Functional Description One standard 50-pin CompactFlash socket for IDE Flash For additional information about this transition module, refer to the TM-PIMC-0001 Transition Module Install and Use (TMPIMCA/IH) manual. 6-24 Computer Group Literature Center Web Site...

  • Page 130: Mcpn750A And Transition Module Connectors

    7Connector Pin Assignments MCPN750A and Transition Module Connectors This chapter summarizes the pin assignments for the following groups of interconnect signals for the MCPN750A base board, the TMCPN710 transition module, and the TM-PIMC-0001 transition module: – MCPN750A CompactPCI Bus Connectors (J1/J2) –...

  • Page 131: Mcpn750A Connector Pin Assignments

    Connector Pin Assignments MCPN750A Connector Pin Assignments The following tables describe connectors used on the MCPN750A base board. Note that the pin assignments for connectors J3, J4, and J5 apply to both transition modules, as well as the MCPN750A. MCPN750A CompactPCI Bus Connectors (J1/J2) The MCPN750A implements a 64-bit CompactPCI interface on connectors J1 and J2.

  • Page 132: Table 7-2. Mcpn750A J2 Compactpci Connector

    MCPN750A Connector Pin Assignments Table 7-1. MCPN750A J1 CompactPCI Connector (Continued) 10 AD21 +3.3V AD20 AD19 CBE3_L IDSEL AD23 AD22 AD26 AD25 AD24 AD30 AD29 AD28 AD27 REQ_L +3.3v AD31 No Connect No Connect RST_L GNT_L (BRSVP1B5) (BRSVP1A5) No Connect...
  • Page 133 Connector Pin Assignments Table 7-2. MCPN750A J2 CompactPCI Connector (Continued) No Connect No Connect No Connect No Connect BRSVP2B16 BRSVP2A16 (DEG_L) (BRSVP2E16) No Connect No Connect No Connect No Connect BRSVP2A15 (FAL_L) (REQ5_L) (GNT5_L) AD35 AD34 AD33 AD32 AD38 AD37...

  • Page 134: Table 7-3. Mcpn750A J3 User I/O Connector

    MCPN750A Connector Pin Assignments Table 7-3. MCPN750A J3 User I/O Connector ROW A ROW B ROW C ROW D ROW E COM3TD +12V -12V COM4RD UDATA1P COM3RD USBV1_OK COM4TD UDATA1N TMCOM1_L MXCLK MXDI MXSYNC_L MXDO COM1TD I2CSCL I2CSDA UDATA0P COM1RD...

  • Page 135: Mcpn750A Connector J4

    USBV0_OK - USB Port 0 Voltage Monitor USBV1_OK - USB Port 1 Voltage Monitor MCPN750A Connector J4 Connector J4 is installed on both the processor board and the transition module for mechanical alignment purposes only. The keying tabs in the Type A connector assist with alignment of pins in the backplane connector during insertion of the boards.

  • Page 136: Mcpn750A Compactpci User I/O Connector (J5)

    Connector J5 is a 110 pin AMP Z-pack 2mm hard metric type B connector. It routes the I/O signals for the PMC2, the IDE port, and the optional ethernet port. Pin assignments (MCPN750A and transition module) are as follows (row F is assigned as ground pins but is not shown in the table): Table 7-4.
  • Page 137 Connector Pin Assignments Signal Descriptions PMCIO: PMC2IO (1:64) - PMC 2 I/O signals 1 through 64 EIDE Primary Port (ATA-2): DMARQA - DMA request DMACKA_L - DMA acknowledge DIORA_L - I/O read DIOWA_L - I/O write DIORDYA - indicates drive ready for I/O DD (15:0) - IDE data lines CS1FXA_L - chip select drive 0 or command register block select CS3FXA_L - chip select drive 1 or command register block select...

  • Page 138: Mcpn750A Pci Mezzanine Card Connectors

    J13/23, J14/24) Four 64-pin connectors (J11/21, 12/22, 13/23 and 14/24 on the MCPN750A) supply the interface between the base board and an optional PCI mezzanine card (PMC). The pin assignments are listed in the tables on the next two pages.

  • Page 139: Table 7-6. Mcpn750A Pci Mezzanine Card Connector

    Connector Pin Assignments Table 7-5. MCPN750A PCI Mezzanine Card Connector (Continued) AD12 AD11 AD10 AD09 AD08 +3.3V C/BE0# AD07 Not Used AD06 AD05 +3.3V Not Used AD04 Not Used +5V (Vio) AD03 Not Used Not Used AD02 AD01 Not Used...
  • Page 140 MCPN750A Connector Pin Assignments Table 7-6. MCPN750A PCI Mezzanine Card Connector (Continued) AD47 AD46 PMCIO35 PMCIO36 AD45 PMCIO37 PMCIO38 +5V (Vio) AD44 PMCIO39 PMCIO40 AD43 AD42 PMCIO41 PMCIO42 AD41 PMCIO43 PMCIO44 AD40 PMCIO45 PMCIO46 AD39 AD38 PMCIO47 PMCIO48 AD37 PMCIO49...

  • Page 141: Mcpn750A 10Baset/100Basetx Connector (J18)

    Connector Pin Assignments MCPN750A 10BaseT/100BaseTx Connector (J18) The 10BaseT/100BaseTx Connector is an RJ45 connector located on the front panel of the MCPN750A SBC. The pin assignments for this connector are as follows: Table 7-7. MCPN750A 10BaseT/100BaseTx Connector J18 AC Terminated...

  • Page 142: Table 7-8. Mcpn750A Debug Connector (J19)

    MCPN750A Connector Pin Assignments Table 7-8. MCPN750A Debug Connector (J19) PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PAPAR0 PAPAR1 PAPAR2 PAPAR3 APE# RSRV# PD10 PD11...
  • Page 143 Connector Pin Assignments Table 7-8. MCPN750A Debug Connector (J19) (Continued) PA20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PD32 PD33 PD34 PD35 PD36 PD37 PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47 PD48 PD49...
  • Page 144 MCPN750A Connector Pin Assignments Table 7-8. MCPN750A Debug Connector (J19) (Continued) TSIZ2 No Connection No Connection No Connection No Connection GLOBAL# No Connection SHARED# DBWO# AACK# +3.3V ARTY# XATS# DRTY# TBST# No Connection TEA# No Connection No Connection DBG# No Connection...
  • Page 145 Connector Pin Assignments Table 7-8. MCPN750A Debug Connector (J19) (Continued) CPUREQ1# INT0 CPUGNT1# MCHK0# INT1#/ SMI# WDT1TO# MCPI1#/WDT2 CKSTPI# L2BR# CKSTPO# L2BG# HALTED L2CLAIM# TLBISYNC# No Connection TBEN No Connection∗ No Connection No Connection∗ No Connection No Connection∗ No Connection...

  • Page 146: Mcpn750A Processor Riscwatch Debug Connector (J6)

    MCPN750A Connector Pin Assignments MCPN750A Processor RISCWatch Debug Connector (J6) A 15-pin header (J6) provides access to the Processor RISCWatch JTAG/COP interface. The pin assignments are listed in the following table. Table 7-9. MCPN750A RISCWatch Debug Connector (J6) No Connect TRST-L No Connect...

  • Page 147: Tmcpn710 Transition Module

    Connector Pin Assignments TMCPN710 Transition Module The following tables summarize the pin assignments of connectors that are specific to MCPN750A modules configured for use with TMCPN710 transition modules. TMCPN710 Transition Module CompactPCI Connectors (J3/J4/J5) Connector J3 is a 95-pin 2mm hard metric type B connector which routes I/O signals for PMC I/O and serial channels.

  • Page 148: Tmcpn710 Transition Module Com1 Connector (J6)

    Transition Module to provide the interface to the COM1 serial port. The TMCOM1 signal jumper, J7 pins 2 and 3 on the Transition Module, must be installed to enable COM1 on the Transition Module. The pin assignments for this connector is as follows: Table 7-10. TMCPN710 COM1 Connector (J6) http://www.motorola.com/computer/literature 7-19...

  • Page 149: Tmcpn710 Transition Module Com2 Connector (J8)

    Connector Pin Assignments TMCPN710 Transition Module COM2 Connector (J8) An RJ45 connector is located on the rear panel of the TMCPN710 Transition Module to provide the interface to the COM2 serial port. The pin assignments for this connector is as follows: Table 7-11.

  • Page 150: Tmcpn710 Transition Module Com4 Header (J14)

    TMCPN710 Transition Module Table 7-12. TMCPN710 COM3/COM4 Headers TMCPN710 Transition Module COM4 Header (J14) Same as above. http://www.motorola.com/computer/literature 7-21...

  • Page 151: Tmcpn710 Transition Module 10Baset/100Basetx Connector (J13)

    Connector Pin Assignments TMCPN710 Transition Module 10BaseT/100BaseTx Connector (J13) The 10BaseT/100BaseTx Connector is an RJ45 connector located on the rear panel of the TMCPN710 Transition Module to support optional ethernet I/O from the Transition Module. To enable this option requires that the proper zero ohm resistors be installed on the processor board.

  • Page 152: Tmcpn710 Transition Module Usb Connectors (J10, J12)

    CompactFLASH plug-in modules. The CompactFLASH interface is connected to the Primary IDE channel. Connector J15 is configured as the Master EIDE interface while J16 is configured as the Slave EIDE interface. The pin assignments for these connectors are as follows: http://www.motorola.com/computer/literature 7-23...

  • Page 153: Table 7-16. Tmcpn710 Compact Flash Ide Connectors

    Connector Pin Assignments Table 7-16. TMCPN710 Compact FLASH IDE Connectors CS1FX1_L No Connect CD2_L CD1_L DD12 DD13 DD14 DD15 CS3FX1_L No Connect DIORA_L DIOWA_L No Connect INTRQA MASTER/SLAVE No Connect DRESET_L IORDY No Connect No Connect DASP PDIAG DD10 7-24 Computer Group Literature Center Web Site...

  • Page 154: Tmcpn710 Transition Module Pmc I/O Connectors (J1/J2)

    PMCIO35 PMCIO5 PMCIO36 PMCIO37 PMCIO6 PMCIO38 PMCIO7 PMCIO39 PMCIO8 PMCIO40 PMCIO9 PMCIO41 PMCIO10 PMCIO42 PMCIO11 PMCIO43 PMCIO12 PMCIO44 PMCIO13 PMCIO45 PMCIO14 PMCIO46 PMCIO15 PMCIO16 PMCIO47 PMCIO17 PMCIO48 PMCIO18 PMCIO49 PMCIO6 PMCIO50 PMCIO51 PMCIO19 PMCIO52 PMCIO20 PMCIO53 PMCIO21 PMCIO54 http://www.motorola.com/computer/literature 7-25...
  • Page 155 Connector Pin Assignments Table 7-17. TMCPN710 PMC 1 and 2 I/O Connector Signal Signal PMCIO22 PMCIO55 PMCIO23 PMCIO56 PMCIO24 PMCIO57 PMCIO25 PMCIO58 PMCIO26 PMCIO59 PMCIO60 PMCIO28 PMCIO61 PMCIO29 PMCIO62 PMCIO30 PMCIO63 PMCIO31 PMCIO64 7-26 Computer Group Literature Center Web Site...

  • Page 156: Tm-Pimc-0001 Transition Module

    TM-PIMC-0001 Transition Module TM-PIMC-0001 Transition Module The following tables summarize the pin assignments of connectors that are specific to MCPN750A modules configured for use with the TM-PIMC- 0001 transition modules. TM-PIMC-0001 CompactPCI User I/O Connector (J3, J4, & J5) Connector J3 is a 95-pin 2mm hard metric type B connector which routes I/O signals for PMC I/O and serial channels.

  • Page 157: Tm-Pimc-0001 Transition Module Com1 Connector (J9)

    COM1DIR jumper (J11) is a two position (three pin) jumper that controls the origin of the serial port. With pins 2-3 jumpered, COM1 from the MCPN750A SBC is enabled (and thereby disables it on the MCPN750A front panel connector). With pins 1-2 jumpered, the connector is redirected to the PMC I/O module 1 (PIM1).

  • Page 158: Tm-Pimc-0001 Transition Module Com2 Connector (J8)

    COM2DIR jumper (J2) is a two position (three pin) jumper that controls the origin of the serial port. With pins 2-3 jumpered, COM2 from the MCPN750A is enabled. With pins 1-2 jumpered, the connector is redirected to the PMC I/O module 2 (PIM2). Refer to the TM-PIMC-0001 Installation Preparation section of Chapter 1 for specific jumper placement information.

  • Page 159: (J12 & J13)

    The signals for the COM3 port and the COM4 port are routed to identical 10-pin headers, which are designated as J12 and J13 respectively on the board. These connections provide rear I/O for the MCPN750A. The pin assignments for these headers are as follows: Table 7-20.

  • Page 160: Tm-Pimc-0001 Transition Module 10Baset/100Basetx Connector (J7)

    The 10BaseT/100BaseTx Connector is an RJ45 connector located on the rear panel of the TM-PIMC-0001 Transition Module to support optional ethernet I/O from the MCPN750A SBC. Appropriate zero ohm resistors must be installed on the processor board to enable this option. The pin assignments for this connector are as follows: Table 7-21.

  • Page 161: Table 7-22. Tm-Pimc-0001 Compactflash Ide Connector (J1)

    Connector Pin Assignments connected to the Primary IDE channel. Connector J1 is configured as the Master EIDE interface. The pin assignments for these connectors are as follows: Table 7-22. TM-PIMC-0001 CompactFLASH IDE Connector (J1) CS1FX1_L No Connect CD2_L CD1_L DD12 DD13 DD14 DD15...

  • Page 162: Tm-Pimc-0001 Transition Module Pmc I/O Connectors (J10, J20, And J14/J24)

    Connector Pin Assignments IN1_DCD +12V IN1_RXD IN1_TXD IN1_DTR IN1_DSR IN1_RTS IN1_CTS +3.3V IN1_RI IN2_DCD IN2_RXD IN2_TXD IN2_DTR IN2_DSR IN2_RTS IN2_CTS IN2_RI Reserved Reserved Reserved +3.3V Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved +3.3V http://www.motorola.com/computer/literature 7-33...

  • Page 163: Table 7-24. Tm-Pimc-0001 Pmc I/O Module 2 (Pim2) - Host I/O Connector Pin Assignments

    Connector Pin Assignments Table 7-23. TM-PIMC-0001 PMC I/O Module 1 (PIM1) - Host I/O Connector Pin Assignments (Continued) Reserved USB0_DATAN USB0_DATAP USB1_VOK USB0_VOK USB1_DATAP USB1_DATAN OUT_RI OUT_DCD OUT_DTR OUT_DSR OUT_CTS +3.3V OUT_RTS OUT_RXD -12V OUT_TXD I2C_CLK I2C_DAT Table 7-24. TM-PIMC-0001 PMC I/O Module 2 (PIM2) - Host I/O Connector Pin Assignments CD1_L +12V...
  • Page 164 PMC I/O modules only use power, ground and the OUT-going serial port pins on the Host I/O connectors. With certain modifications, it is possible for a host I/O module to use all pins except the OUT-going serial port. http://www.motorola.com/computer/literature 7-35...
  • Page 165 Connector Pin Assignments Table 7-25. PMC I/O Modules 1 and 2 (PIM1 and PIM2) - PMC I/O Connector Pin Assignments J14/J24 PMC IO1 PMC IO2 PMC IO3 PMC IO4 PMC IO5 PMC IO6 PMC IO7 PMC IO8 PMC IO9 PMC IO10 PMC IO11 PMC IO12 PMC IO13...
  • Page 166 PMC IO61 PMC IO62 PMC IO63 PMC IO64 Note Pin meaning for the PMC I/O connector is defined entirely by the PMC residing on the host. A host I/O module does not use any pins on this connector. http://www.motorola.com/computer/literature 7-37...
  • Page 167 Connector Pin Assignments 7-38 Computer Group Literature Center Web Site...

  • Page 168: Appendix A Specifications

    MCPN750A base boards. Subsequent sections detail cooling requirements and FCC compliance. A complete functional description of the MCPN750A base boards appears in Chapter 3. Specifications for the optional PCI mezzanines can be found in the documentation for those modules.

  • Page 169: Cooling Requirements

    CompactPCI chassis and supplied with 55 degree C air flow at sea level. Tests were conducted with a Motorola CPX8216 system. Case temperatures of critical, high power density integrated circuits are monitored to ensure component vendors’...

  • Page 170: Emc Compliance

    EMC Compliance EMC Compliance The MCPN750A Single Board Computer was tested in an EMC-compliant chassis and meets the requirements for EN55022 Class B equipment. Compliance was achieved under the following conditions: Shielded cables on all external I/O ports. Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel.
  • Page 171 Specifications Computer Group Literature Center Web Site...

  • Page 172: Motorola Computer Group Documents

    BRelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature...

  • Page 173: Manufacturers' Documents

    Telephone: (800) 441-2447 or (303) 675-2140 FAX: (602) 994-6430 or (303) 675-2150 WebSite: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com MPC750 RISC Microprocessor User’s Manual MPC750UM/AD Literature Distribution Center for Motorola Semiconductor Products Telephone: (800) 441-2447 FAX: (602) 994-6430 or (303) 675-2150 WebSite: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com MPR604UMU-01 IBM Microelectronics Web Site: http://www.chips.ibm.com/techlib/products/powerpc/manuals...
  • Page 174 May 13, 1997 VIA Technologies, Inc. http://www.viatech.com/pdf/productinfo/586b.pdf ATMELSerial EEPROM Data Sheet AT24C04A Atmel Corporation Rev 0976B-07/98 Must request documentation at: http://www.atmel.com/atmel/support/ Texas Instruments TI16C550C Asynchronous Communications Element (ACE) - SLLS177E Data Sheet March 1994, Texas Instruments Revised April 1998 http://www.ti.com/sc.docs/products/analog/ti16c550c.html http://www.motorola.com/computer/literature...

  • Page 175: Related Specifications

    Related Documentation Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
  • Page 176 Publication Document Title and Source Number PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: (800) 441-2447 FAX: (602) 994-6430 or (303) 675-2150 http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com ISBN 1-55860-394-8 Morgan Kaufmann Publishers, Inc.
  • Page 177 Related Documentation Table B-3. Related Specifications (Continued) Publication Document Title and Source Number Compact PCI Specification CPCI Rev. 2.1 Dated 9/2/97 PCI-to-PCI Bridge Specification Rev. 1.02 PCI-ISA Specification Rev. 2.0 CompactPCI Hot Swap Specification (Draft) PICMG 2.1 DO.91 Dated 2/5/98 PCI Industrial Manufacturers Group (PICMG) http://www.picmg.com/ Computer Group Literature Center Web Site...
  • Page 178 1-10 address decoding 21554 Bridge chip board failure light 6-20 advantages big-endian 2-12 block diagram Abort/Reset switch 6-19 MCPN750A address board ethernet configuration address decoding board failure LED 6-20 with 21554 Board Information Block arbitration hardware display PCI bus masters...
  • Page 179 10BaseT/100BaseT 7-12, 7-22 COM1 restrictions 1-13 10BaseT/100BaseT for TM-PIMC-0001 COM1 signal routing 1-13 7-31 COM1/COM2 for I/O routing, MCPN750A on TM-PIMC-0001 transition module connector (transition) 1-18 for COM1 port 7-19, 7-28 COM2 for COM2 port 7-20, 7-29 jumper setting J2 on TM-PIMC-0001...
  • Page 180 Raven ASIC 2-13 purpose 1-20 PCI domain 2-13 Help processor/memory domain 2-12 for list of PPCBug commands ENV command help command 3-10 environmental parameters Hot Swap equipment requirements status LED 6-20 for MCPN750A hot swap components 6-14 ESD precautions http://www.mcg.mot.com/literature IN-3...
  • Page 181 TM-PIMC-0001 7-30 Initialize Memory J13 connector remote start for TMCPN710 7-22 initializing devices for TM-PIMC-0001 7-30 install J14 header PMC modules on MCPN750A 1-21 on TMCPN710 7-21 installation J15 connector base board 1-21 for TMCPN710 7-23 installing J16 connector...
  • Page 182 J9 connector features, hardware for TM-PIMC-0001 7-28 operating modes 1-10 jumper headers power requirements 1-31 MCPN750 base board MCPN750A assembly installation 1-24 jumper J11 MCPN750A description on TM-PIMC-0001 1-18 memory map jumper J2 default on TM-PIMC-0001 1-18...
  • Page 183 Index voltage 1-21 NETboot enable PMC connectors Network Auto Boot enable MCPN750A NIOT command PMC expansion restrictions PMC function Non-Volatile RAM (NVRAM) PMC I/O as containing PPCBug parameters as transition module feature 6-23 PMC instal 1-21 on-board battery PMC modules...
  • Page 184 Auto-Initialize of NVRAM Header En- prompt, debugger 3-11 able PRST Bug or System explained as reset source 2-10 DRAM Parity Enable 4-10 push button reset 2-11 DRAM Speed in NANO Seconds Field Service Menu Enable explained for timer functions 6-11 L2 Cache Parity Enable 4-10 Raven ASIC...
  • Page 185 Index RF emissions jumper setting (J8) minimized on TMCPN710 1-29 startup overview proper grounding 1-25 switch RJ45 connector from one PPCBug directory to another on serial ports 1 and 2 1-13 ROM/Flash Bank A or B System Call Handler mapping PPCBug subroutine ROMboot enable system clocks...
  • Page 186 MCPN750A 1-31 VT82C586B Peripheral Bus Controller Watchdog timer as part of M48T559 6-15 as reset source 2-10 as type of interrupt watchdog timer function 6-11 Watchdog Timer reset 2-11 Watchdog timers as part of Raven 6-15 WDT1 Raven Watchdog timer...
  • Page 187 Index IN-10 Computer Group Literature Center Web Site...

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