Table of Contents
Advertisement
12.1.2 Nonmaskable Interrupt Request
A nonmaskable interrupt request is input to the NMI pin. When a valid edge, specified by bit 0 (ESNMI) of external
interrupt mode register 0 (INTM0), is input to the NMI pin, an interrupt request is generated.
A nonmaskable interrupt request is accepted unconditionally, even in an interrupt disabled state. In this case,
interrupt priority control is not applied; the nonmaskable interrupt request takes precedence over all other
interrupts.
12.1.3 Maskable Interrupt Request
Maskable interrupt requests can be masked by setting the interrupt mask register (MK0). The IE flag in the PSW
can specify whether to enable or disable all the maskable interrupts simultaneously.
A default priority is assigned to each maskable interrupt request as shown in Table 12-2, so that, when two or more
interrupts having the same priority occur at the same time, which interrupt takes precedence is determined. The
interrupts can be divided into two groups by the priority specification flag register (PR0); a group of interrupts with
higher priority and a group of interrupts with lower priority, so that multiple-interrupt handling can be achieved.
However, the macro service is accepted independently of the priority control and the IE flag.
12.1.4 Selecting an Interrupt Source
Interrupts INTP4 and INTC30 cannot be used at the same time, because these interrupts share the same vector
table, interrupt request flags, and other control flags. Therefore, either INTP4 or INTC30 must be selected by
software. The same holds true of a pair of INTP5 and INTAD. A selected interrupt request source is given the right
to use the vector table, interrupt request flags (PIFn; n = 4 or 5), interrupt mask flags (PMKn; n = 4 or 5), interrupt
service mode flags (PISMn; n = 4 or 5), and priority specification flags (PPRn; n = 4 or 5) exclusively, thus generating
the corresponding interrupt and macro service. The other interrupt request sources cannot use these resources,
and therefore cannot generate an interrupt or macro service.
The other types of interrupts have a dedicated vector table and control flags, and therefore need not be selected.
(1) Selecting INTP4 or INTC30
Interrupt INTP4 or INTC30 is selected by the ES40 and ES41 bits of external mode register 1 (INTM1).
Both 8-bit manipulation instruction and bit manipulation instruction can be used to read data from and write
data to the INTM1 register. The format of this register is shown in Fig. 12-1.
When the RESET signal is input, the register is reset to 00H, and INTP4 occurs on the falling edge at the INTP4
pin.
7
INTM1
0
Fig. 12-1 INTM1 Register Format
6
5
4
3
2
0
ES51
ES50
ES41
ES40
ES41
ES40
Selects interrupt request source
Selects INTP4 (which occurs at falling edge
0
0
for INTP4 pin input)
Selects INTP4 (which occurs at rising edge
0
1
for INTP4 pin input)
Selects INTC30 (which occurs when TM3
1
0
coincides with CR30)
Selects INTP4 (which occurs at both rising
1
1
and falling edge for INTP4 pin input)
Chapter 12 Interrupt Functions
1
0
ES31
ES30
Specifies edges to be detected
on P24 and P26 pins (See Fig. 11-2)
12
303
Advertisement
Table of Contents
