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UX-P5R
LC72723(IC3):RDS
1.
Pin Assignment
Block diagram
2.
Vdda
REFERENCE
VOLTAGE
Vssa
ANTIALIASING
MPXIN
FILTER
TEST
TEST
3. Pin functions
Pin
Symbol
I/O
No.
1
O
VREF
MPXIN
I
2
Vdda
3
Vssa
4
O
5
FLOUT
6
CIN
I
TEST
I
7
8
XOUT
O
9
XIN
I
Vssd
10
Vddd
11
I
12
MODE
13
RST
I
14
O
RDDA
RDCL
I/O
15
RDS-ID
16
O
READY
1-32
VREF
FLOUT CIN
57kHz
BPF
SMOOTHING
(SCF)
FILTER
CLK(4.332MHz)
OSC
XIN
Reference voltage output (Vdda/2)
Baseband (multiplexed) signal input
Analog power supply (+5V)
Analog ground
Subcarrier input (filter output)
Subcarrier input (comparator input)
Test input
Crystal oscillator output (4.332MHz)
Crystal oscillator input (exeternal reference input)
Digtal ground
Digtal power supply
Read mode setting (0:master,1:slave)
RDS-ID/RAM reset (positive polarity)
RDS data output
RDS clock output (master mode)/RDS clock input (slave mode)
RDS-ID/READY output (negative polarity)
PLL
(57kHz)
VREF
XDUT
Function
CLOCK
Vddd
RECOVERY
(1187.5kHz)
DATA
DECODER
RAM
MDDE
(128-bits)
RDS-ID
RDS-ID/
DETECT
READY
Vssd
RDDA
RDCL
RST
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